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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of the ConnX Family with B10 and B20

In this week’s Whiteboard Wednesdays, Pierre-Xavier Thomas introduces the B10 and…

• less than a min read
Whiteboard Wednesdays , ConnX

Analog/Custom Design

Virtuosity: New Flexible Subwindows

Plots in Cadence Virtuoso Visualization and Analysis can be plotted in a window or…

• 3 min read
ICADVM18.1 , subwindows , waveforms , Virtuoso Analog Design Environment , ViVA , Virtuosity , plotting templates , Custom IC Design , IC6.1.8

Breakfast Bytes

Tensilica ConnX B20 for 5G, and Automotive Radar/Lidar

I'm sure you've noticed that there is a lot of talk about 5G in the air. Well, "in…

• 6 min read
5G , connx b20 , lidar , radar , Tensilica

The India Circuit

Opportunities for India in Industry 4.0

The India Electronics and Semiconductor Association (IESA) the industry body that…

• 3 min read
Vision Summit , Industry 4.0 , gig economy , IESA

Breakfast Bytes

OFC: The Optical Fiber Communication Conference

OFC is the Optical Fiber Communication Conference and Exposition (yes, some initials…

• 3 min read
optical fiber , photonics

Breakfast Bytes

Sunday Brunch Video for 24th February 2019

https://youtu.be/uUWiysEM4jM Made on the top of building 10 (camera Sean) Monday…

• less than a min read
sunday brunch , video

PCB、IC封装：设计与仿真分析

DesignCon：Cadence与IBM联手讲授高级IBIS-AMI技术

本文翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章 "DesignCon: Cadence teaches AMI…

• less than a min read
Chinese blog , DesignCon , AMI , IBIS , IBIS-AMI , 中文 , SerDes , Sigrity

Breakfast Bytes

Badges—Not Just for Scouts Anymore

Were you a Boy Scout? Or a Girl Guide or Girl Scout? What badges did you earn? Not…

• 3 min read
digital badge , training , training bytes

System, PCB, & Package Design 

Simulation of LPDDR4X Interface: What Designers Need to Know and Do

System designers are familiar with standard DDR4 RAM components but with the demands…

• 2 min read
Serial link analysis , SI , LPDDR4 , DesignCon , DesignCon 2019 , Signal Integrity , Channel simulation , Sigrity , BER , SystemSI

Analog/Custom Design

Verifying Power Intent in Analog and Mixed-Signal Designs Using Formal Methods

Analog and Mixed-signal (AMS) designs are increasingly using active power management…

• 2 min read
AMS , Virtuoso Schematic Editor , Low Power , virtuoso power manager , Virtuoso-AMS , mixed signal design , mixed signal solution , Virtuoso , low-power design , mixed signal , mixed-signal verification

Analog/Custom Design

Virtuosity: A Smart Extracted View

The Cadence Quantus Smart View is the next generation of the Extracted View in the…

• 4 min read
Smart View , PAD , ICADVM18.1 , ADE Explorer , Virtuoso , Virtuosity , Quantus , IC6.1.8 , parasitics , ADE Assembler , Virtuoso Layout Suite XL

Breakfast Bytes

Who Is Green Hills?

Cadence announced during their recent quarterly earnings announcement and call that…

• 5 min read
vast systems technology , Integrity , embedded software , Green Hills , Virtutech

Digital Design

Pattern Technology Applied to Machine Learning-based Hotspot Prediction

I have been working on DFM solutions for (too) many years and the objective hasn…

• 1 min read
pattern analysis , machine learning , silicon learning , signoff , yield , design for manufacturing , DFM

Whiteboard Wednesdays

Whiteboard Wednesdays - An Introduction to IC Test and Modus

In this week's Whiteboard Wednesdays video, distinguished Engineer Rohit Kapur introduces…

• less than a min read
DFT , Whiteboard Wednesdays , modus , Test

Breakfast Bytes

Ronto and Quecto Are Not Cheeses

The International Bureau of Weights and Measures (its initials are BIPM because it…

• 5 min read
ronna , ronto , quecca , quecto , bipm

PCB、IC封装：设计与仿真分析

什么是COM/JCOM信道合规技术

在当今这个数以十计/两位数Gbps的数据时代里， 工程师的工作越来越不容易，正确地设计并表征系统以符合不断刷新的业内标准搞得大家焦头烂额，不仅要对高速串行链路及其所有损耗进行仿真…

• less than a min read
JCOM信道合规 , SI , Chinese blog , 设计合规 , JCOM , COM/JCOM , COM , 中文 , Sigrity , Channel Operating Margin(COM) , SystemSI , 信号完整性 , 通道裕量

System, PCB, & Package Design 

Take a lesson from the Amish...

“Time to design completion” is almost always the primary metric and the cause for…

• 1 min read
collaboration , SiP , packaging , Symphony , IC package design

Breakfast Bytes

Breakfast Buffet for January 2019

https://youtu.be/4N5bx3eR_9U The three highlighted posts for January were: Breakfast…

• less than a min read
predictions , deep learning , alphazero , persistent memory

Breakfast Bytes

All the Ps: the Photonics PDK Panel

At DesignCon at the end of January, there was a panel on photonics. The title was…

• 7 min read
Lumerical , silicon photonics , photonics
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