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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

Analog/Custom Design

SPECTRE 20.1 Release Now Available

The SPECTRE 20.1 release is now available.

• 1 min read
spectre aps , Spectre MS , Distributed HB , Spectre , XDP , Spectre X Simulator

Breakfast Bytes

Breakfast Bytes Update: DATE, OpenROAD, Starlink

This is one of my occasional posts where I update some posts that I covered earlier…

• 4 min read
openroad , update , starlink

カスタムIC／ミックスシグナル

Virtuosity: 新しい柔軟なサブウィンドウ

Cadence® Virtuoso® Visualization and Analysis でのプロットは、ウィンドウまたはサブウィンドウにプロットすることができます…

• less than a min read
ICADVM18.1 , subwindows , waveforms , Virtuoso Analog Design Environment , ViVA , Virtuosity , plotting templates , japanese blog , Custom IC Design , IC6.1.8

Breakfast Bytes

Breakfast Bytes Update: Learning & Support, Undersea Datacenter

This is one of my occasional posts where I update some posts that I covered earlier…

• 3 min read
microsoft , project natick , support app , Support , training , update

Breakfast Bytes

GTC 2020

Recently, GLOBALFOUNDRIES held this year's technology conference GTC. Of course,…

• 5 min read
GTC , gtc 2020 , GlobalFoundries

Analog/Custom Design

Spectre Tech Tips: Spectre X Update

About a year ago, we released Spectre X in the SPECTRE 19.1 base release. Since then…

• 4 min read
+preset , LX mode , Distributed HB , XDP , spectre x

System, PCB, & Package Design 

BoardSurfers: Rev Up Your Designs Using Color Themes in Allegro 3D Canvas

You will agree if I say that the right use of color gets attention, enhances clarity…

• 4 min read
PCB , 3D Canvas , APD , Layout , 17.4-2019 , 3D , PCB design , Allegro PCB Editor

The India Circuit

Ankita Kanojia: A Story of Grit and Determination

At Cadence, giving back to the communities where we live and work is an integral…

• 3 min read
CadenceCares , CadenceScholarshipProgram , cadence , WomenEmpowerment , GirlPower

System, PCB, & Package Design 

IC Packagers: The Importance of Proper DC Net Identification

It may surprise some of you, but I often receive databases in which the power and…

• 5 min read
IC Packaging and SiP , Allegro Package Designer , 17.4-2019

Breakfast Bytes

NXP Glows in Tensilica HiFi

One trend that many people have remarked on, is that neural network inference is…

• 2 min read
DSP , hifi 4 , NXP , HiFi , Tensilica , glow , neural network , nnlib

カスタムIC／ミックスシグナル

Start Your Engines: ミックスシグナル・シミュレーションを高速化するためのヒント

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• less than a min read
mixed signal design , mixed-signal methodology , AMS Designer , analog behavioral models , mixed signal , japanese blog , wreal , real number models , SPICE , AMS Verification , vams , mixed-signal verification

Digital Design

What’s inside Joules Graphical User Interface!!

Power is HOT and it touches everything and everybody! But we can help with power…

• less than a min read
gui , Joules , Power Analysis

Breakfast Bytes

The CHIPS Alliance

On September 17, there was a meeting of the CHIPS Alliance. It was online, of course…

• 4 min read
open source eda , open source hardware , open source , chips alliance

Breakfast Bytes

Sunday Brunch Video for 27th September 2020

https://youtu.be/EUDdGqdmTUU Made in "the Alps" Monday: Complete RF Solution: Think…

• less than a min read
sunday brunch

Breakfast Bytes

CadenceLIVE Europe 2020 Preview

Normally, in May, I'd have been off to Unterschleißheim, a suburb of Munich where…

• 3 min read
CadenceLive Europe , cadencelive

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: クロス・ファブリックな電磁界解析 - IC、パッケージ、ボードのデータをマージするという面倒な作業をなくす

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Virtuoso ICADVM18.1 , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF , Electromagnetic analysis , Virtuoso , japanese blog , Custom IC Design , Virtuoso Layout Suite

カスタムIC／ミックスシグナル

Virtuosity: What's New in Run Plan – パート IV

このブログは、what’s new blogシリーズの一部です。このブログの関連リソースのセクションに、このシリーズの以前のブログへのリンクがあります。ユーザーが最新の設計検証の複雑さを克服できるようにするために…

• 1 min read
Virtuoso Analog Design Environment , Virtuoso , Virtuosity , Run Plan , japanese blog , Custom IC Design , Custom IC , IC6.1.8 , Assembler , ADE Assembler

Analog/Custom Design

Virtuosity: Usability Enhancements in Simulation Driven Routing

Since IC6.1.8 and ICADVM18.1 was released, we have continued our drive to improve…

• 4 min read
Interactive Routing , EAD , ICADVM18.1 , electrically aware design , Virtuoso Layout EXL , Layout Suite , Virtuoso , Virtuosity , simulation driven interactive routing , mixed signal , usability , Custom IC Design , Custom IC

Breakfast Bytes

Should the Government Adopt Commercial Best Practice?

There is something called Betteridge's Law of Headlines that if a headline or title…

• 4 min read
prototyping , Aerospace , Protium , Palladium , Emulation , commercial best practice , aviation week
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