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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: 標準ライブラリコンポーネントの定義

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Libimport , Unified Library , JEDEC , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Virtuoso MultiTech , Package Design in Virtuoso , Allegro Package Designer Plus , BGA , Allegro Package Designer , die , Virtuoso , ICADVM20.1 , Cadence SiP Layout , japanese blog , Custom IC Design , Custom IC , Allegro , VMM

RF /マイクロ波設計

Cadence AWR Design Environment E-ニュースレター(2020年12月)

日本語翻訳版をお届けします。ぜひ最新の製品に関する最新の情報をご確認ください。 このニュースレターの英語版は こちら です。 Cadence AWR Design…

• less than a min read
RF , awr , japanese blog

System, PCB, & Package Design 

IC Packagers: Copying Objects across Layers and Classes

Some items are useless on multiple levels. The most common multi-class pairing is…

• 5 min read
IC Packaging and SiP Design , 17.4 , Allegro Package Designer , 17.4-2019

System, PCB, & Package Design 

(P)SpiceItUp: Five Ways of Finding the Right PSpice A/D Component

When you are designing a schematic, you want to focus on the accuracy and performance…

• 3 min read
17.4 , OrCAD Capture , PSpiceA/D , Capture CIS , 17.4-2019 , OrCAD

カスタムIC／ミックスシグナル

Virtuosity: Conserve Power— インデザイン・チェックの実行

Conserve Powerは、ローパワー検証の世界を垣間見ることができるブログ・シリーズです。デザインのパワーインテントを指定し管理することができるVirtuoso…

• less than a min read
In-Design Checks , Low Power , virtuoso power manager , Schematic XL , in-design , VPM , Schematic Editor , ICADVM20.1 , UPF , Power Manager , mixed signal , japanese blog , Liberty , Custom IC Design

RF /マイクロ波設計

2021年1月 オンラインワークショップ - 増幅器設計の機能を体験

2021年1月 オンラインワークショップ ケイデンスオンラインセミナーでは、高周波設計のソリューションを定期的に紹介しています。今回はソフトウェアを利用しながら…

• less than a min read
RF , awr , japanese blog

Breakfast Bytes

Off Topic: "Beam Me Up, Scotty" and Other Things Nobody Said

T his is my end-of-year off-topic holiday post, traditional before a break or a holiday…

• 6 min read
offtopic

カスタムIC／ミックスシグナル

Virtuoso Video Diary: デジタル信号のユーザビリティ改善

私達は、ユーザビリティに対してのアイデアが製品を使いやすく、アクセスをさらに容易にし、視覚的に魅力的なものにする世界に住んでいます。製品の使いやすさを向上させるために…

• less than a min read
Mnemonic Map , Cadence blogs , ICADVM18.1 , simvision , analog , Virtuoso Visualization and Analysis XL , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Virtuoso Video Diary , ICADVM20.1 , Configure Mnemonics , usability , japanese blog , Custom IC , IC6.1.8

Digital Design

Do You Know Multibit Cells Could Help You Reduce Clock-Tree Power and Alleviate Wiring…

Hi everyone, Searching for yet another method to improve the QoR of your design…

• 3 min read
blended training , Genus , training bytes , Digital Implementation , online training , Cadence support

Breakfast Bytes

Breakfast Nibbles: How Did My 2020 Predictions Turn Out?

Every year I make a few predictions about trends for the coming year. I will be doing…

• 5 min read
5G , Automotive , predictions , cloud , more than Moore , cadence cloud , autonomous vehicles

定制IC芯片设计

Virtuoso Meets Maxwell: Clarity 与有限元方法结合

本文将介绍Clarity 的一些功能，当你需要使用基于FEM的电磁解算器用于 Virtuoso RF 解决方案时，Clarity 将会是您 的最佳选择！

• 1 min read
EM Analysis , Chinese blog , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , Clarity 3D , Electromagnetic analysis , ICADVM20.1 , Finite Element Method , Virtuoso Layout Suite , clarity

Digital Design

Library Characterization Tidbits: Bidding Adieu to 2020

This year all our “regular” routines were shaken up by COVID-19, which brought along…

• 2 min read
library characterization , Library Characterization Tidbit , Digital Implementation , Liberate Characterization Portfolio

カスタムIC／ミックスシグナル

Virtuosity: Voltus-Fi-XL FAQ — よくある質問とその回答

読者のみなさん、こんにちは！ Voltus-Fiに関する蒸留された知識をお探しなら、正しいページにお立ち寄りいただきました！ 何年にもわたって好奇心を持ち続け、さまざまなプラットフォームでのVoltus…

• less than a min read
ICADVM18.1 , Voltus-Fi-XL , PGV , Electromagnetic analysis , japanese blog , IR drop , Custom IC Design , IC6.1.8 , EMIR

Analog/Custom Design

Virtuosity: Moving Along the Least-Resistive Path in Voltus-Fi

Do you want to know how discovering the path of least resistance for the devices…

• 4 min read
Voltus-Fi , electromigration , EMIR Analysis , power grid , Voltus-Fi-XL , Virtuoso , voltage drop , ICADVM20.1 , LRP , Custom IC Design , Custom IC , IC6.1.8

Life at Cadence

Chiplets and Heterogeneous Packaging Are Changing System Design and Analysis

In the domain of electronic product design, solely relying on process shrink as the…

• 10 min read
chiplets , 3D-IC , heterogeneous integration

Breakfast Bytes

RISC-V: The Next Ten Years

The annual RISC-V Summit (virtual, of course) was in early December. You can read…

• 10 min read
risc-v

Analog/Custom Design

Spectre Tech Tips: Increasing Performance and Capacity Using Spectre X Distributed…

The Spectre X distributed simulation is an extension to the multithreaded simulation…

• 5 min read
multithreaded simulation , ppn , Multi-Core , XDP , spectre x , Spectre X distributed simulation , multithreaded

RF Engineering

μWaveRiders: Cadence AWR EM Simulators Solve Complex RF/Microwave Structures for…

RF designers increasingly rely on electromagnetic (EM) simulations to characterize…

• 3 min read
RF , AWR simulation , AWR Analyst , AWR Design Environment , awr , EM simulation , AWR EM Simulators , Electromagnetic analysis , Electromagnetic (EM) , AWR AXIEM , Analyst 3D FEM EM Simulator , AXIEM 3D Planar Simulator , simulation

Digital Design

Wondering What to Do During the Winter Staycation? How about Learning Something New…

We just recently released a training course that we are excited to tell you about…

• 1 min read
conformal , Genus , Tempus , modus , Voltus , Digital Implementation , Innovus
CDNS - Fix Layout Hompage