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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
cdns - all_blogs_categories

Blog - Post List
Latest blogs

SoC and IP

Designing for the Future - Managing the Impact of Moore's Law

With Moore’s Law, the industry assumes that when you go from one geometry to the…

• 3 min read
Design IP , IP , LPDDR , PCIe Gen4 , MIPI , USB , SerDes

Breakfast Bytes

Vision Q7 DSP: Real-Time Vision and AI at the Edge

At CDNLive EMEA, we announced the latest member of the Tensilica family at the press…

• 4 min read
vision Q7 , Tensilica

Whiteboard Wednesdays

Whiteboard Wednesdays - Featuring the new Tensilica Vision Q7 DSP IP for Vision and…

In this week’s Whiteboard Wednesdays video, Pulin Desai talks about the latest addition…

• less than a min read
Whiteboard Wednesdays , Vision Q7 DSP

Analog/Custom Design

Virtuosity: Did My Checks Pass or Did They Not Run?

If you've ever tried to run the Checks/Asserts flow in Virtuoso ADE Assembler and…

• 2 min read
ADE Explorer , Virtuosity , Custom IC Design , ADE Assembler

Breakfast Bytes

After Meltdown and Spectre

At the recent Linley Spring Microprocessor Conference, the second day's keynote was…

• 7 min read
meltdown , processor , Linley , Spectre

Digital Design

LIBERATE 19.2 Base Release Now Available

The LIBERATE 19.2 production release is now available for download at Cadence Downloads…

• 2 min read
Liberate AMS , Bolt Job Distribution , Liberate Release Blog , Cadence blogs , characterization , liberate trio , LIBERATE19.2 , Liberate LV , Health Incident Report , Liberate Variety , Liberate MX , Digital Implementation , Ascava Distillation , Liberate , Characterization Portfolio , Liberty , Leakage Power Management

Breakfast Bytes

Bob Smith on ESD Alliance, ES Design West...with Wine

I talked to Bob Smith recently about what's coming up in the world of the ESD Alliance…

• 4 min read
semicon , semi , es design west , esd alliance

Breakfast Bytes

Sunday Brunch Video for 12th May 2019

https://youtu.be/E61e34IbaRE Made at CDNLuve EMEA (camera Andrea Huse) Monday: Statistical…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

通过人工神经网络探讨信号完整性的未来

想象一下，如果电脑或机器人可以完成所有枯燥乏味的工作，我们就能享受生活、做更多有意义的事。这些绝对是许多学术界、工业界研究人员的愿望。工程师的最终梦想是，按下一个…

• 1 min read
SI , Chinese blog , 人工神经网络 , 中文 , Sigrity , SystemSI , 信号完整性

Digital Design

HLS Optimizations You Can't Do By Hand

In my previous blog post , I talked about the Quality-of-Results (QoR) that are achievable…

• 3 min read
High-Level Synthesis , Stratus , SystemC , HLS

Breakfast Bytes

150th Anniversary of the Transcontinental Railroad

150 years ago, technology meant railroads, not semiconductors. I mean, precisely…

• 4 min read
railroad

System, PCB, & Package Design 

Finally, A Certified and Correlated Reference Flow for Advanced Package Designs

As transistor device scaling gets closer and closer to physical limits, more and…

• 2 min read
advance packaging , Silicon-interposer 2.5D package-based test , reference flow , Samsung , CDNLive 2019 , package design , DesignCon 2019 , FO-PLP , Sigrity , CDNLive San Jose , Package signoff , Advanced Package design and sign-off reference flow

Analog/Custom Design

Virtuosity: The Top 3 Post-Layout Enhancements in Analog Design Environment

Have you ever wanted to sweep DSPF files across corners, plot terminal current and…

• 4 min read
ADE Explorer , post-layout , DSPF , Virtuoso Analog Design Environment , postlayout , Virtuosity , ADE Assembler

Breakfast Bytes

Intel at Linley

At the recent Linley Spring Microprocessor Conference, there were two presentations…

• 4 min read
Intel , Linley

Verification

Concurrent Actions in Specman: Part 2

In the previous blog: Concurrent Actions in Specman , we discussed the existing options…

• 4 min read
Specman , Specman/e , Specman e , concurrency , specman elite

Breakfast Bytes

How Do Out-of-Order Processors Work Anyway?

I've been meaning to write a post on how out-of-order processors work, but one challenge…

• 8 min read
processor , Linley , red hat , instruction set architecture

Whiteboard Wednesdays

Whiteboard Wednesdays - Limitations of Scan Compression QoR

In this week's Whiteboard Wednesdays video, Scan Compression reduces the digital…

• less than a min read
Whiteboard Wednesdays , modus , Scan Compression

The India Circuit

A Special Day for Cadence India

A few days ago, Cadence Bangalore, Noida and Pune sites had the opportunity to participate…

• 1 min read
One Cadence-One Team , Volunteer Time Off , Cadence India , Rise Against Hunger

Breakfast Bytes

JasperGold: the Next Generation

Formal verification has gone through a number of eras. In the early 1990s, it was…

• 3 min read
formal , machine learning , JasperGold , Formal verification , verification
CDNS - Fix Layout Hompage