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Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Virtuosity: Virtuoso Design Intent Notes Now Speak Many Languages

Starting with ICADVM20.1 ISR20, you can write Design Intent notes in languages that…

• 2 min read
Virtuoso Design Intent , Virtuoso Schematic XL , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , ICADVM20.1 , Constraints , design intent , Custom IC Design , Custom IC , Virtuoso Layout Suite XL

Breakfast Bytes

Happy 10th Birthday ISO 26262

Today is the 10th anniversary of ISO 26262. It was first published on 11th November…

• 3 min read
Automotive , functional safety , midas , ISO 26262

Breakfast Bytes

Announcing Jasper C2RTL App: Formal for Algorithmic Designs

Today is the first day of the Jasper User Group (unofficially known as JUG to attendees…

• 2 min read
Jasper User Group , c2rtl , formal , Jasper , JasperGold

定制IC芯片设计

Virtuoso Meets Maxwell: 标准库组件的定义

The Allegro Package Designer 产品线提供IC 封装从创意到生产所需的一切，它可以从Virtuoso环境通过Virtuoso MultiTech…

• 1 min read
Libimport , Unified Library , JEDEC , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Virtuoso MultiTech , Package Design in Virtuoso , Allegro Package Designer Plus , Allegro Package Designer , die , Virtuoso , ICADVM20.1 , Cadence SiP Layout , Custom IC Design , Custom IC , Allegro , Chinese blogs , VMM

PCB設計／ICパッケージ設計

BoardSurfers: Allegro PCB Editorを17.4-2019 Hotfix 019以上にバージョンアップするべき理由とは

Cadence OrCAD and Allegro 17.4-2019 Hotfix 019（17.4-QIR3） は7月中旬にリリースされました。、現在は更に新しいHotfixがダウンロード可能です…

• 1 min read
PCB , 17.4 , BoardSurfers , PCB Editor , 17.4-2019 , 17.4-2021 , japanese blog , Allegro PCB Editor , 17.4-QIR3 , Allegro

Breakfast Bytes

Last-Mover Advantage

I was reminded recently of a video/transcript that I remember coming across when…

• 6 min read
startups , tesla , peter thiel

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Sigrity X the Next-Generation Signal and Power Integrity…

Explore how Sigrity X, the next-generation signal and power integrity (SI/PI) solution…

• 5 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , SPEEDEM , XcitePI , Sigrity X , Voltus IC Power Integrity Solution , IBIS Modeling , Sigrity PowerSI , Power Integrity , Sigrity OptimizePI , IBIS-AMI , Signal Integrity , Sigrity SystemSI , Sigrity XtractIM , Sigrity PowerDC , Clarity 3D Solver , T2B , Allegro PCB Designer

Digital Design

Voltus Voice: Hierarchical Power Integrity Analysis—Everything You Need to Know About…

In part 2 of our "Hierarchical Power Integrity Analysis" blog series, we discuss…

• 5 min read
Voltus XM , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , xPGV models , Power Integrity , hierarchical power integrity analysis , IRdrop , Extreme Modeling , Full-Chip

Breakfast Bytes

Reality in Your Glasses

Despite all the recent noise about the Metaverse (and Facebook changing its company…

• 5 min read
rayban , Facebook , virtual reality , augmented reality , meta

中文技术专区

持续推进摩尔时代的IC设计艺术

2021 年 11 月 3 日，由 ASPENCORE 主办的“2021 全球高科技领袖论坛 - 全球 CEO 峰会&全球分销与供应链领袖峰会”于深圳举行。Cadence…

FormerMember • less than a min read
3D IC , Integrity , moore's law

The India Circuit

Mentor Story: Rajesh Swami Narayanan - Cadence Scholarship Program

The Cadence Scholarship Program is the flagship CSR program of Cadence India, introduced…

• 2 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India

PCB、IC封装：设计与仿真分析

计算航空航天和计算流体力学的发展与未来

本文翻译自Cadence “Computational Fluid Dynamics”专栏作者文章“ The Evolution of Computational…

• 2 min read
网格划分 , CFD , Chinese blog , 计算流体力学 , 流体力学 , FLO22 , Pointwise , CFD应用 , 中文 , NUMECA , 网格 , 航空航天

PCB解析／ICパッケージ解析

Sigrity / Systems Analysis 2021.1 HF3リリース(2021年9月) - 新機能ハイライト

Sigrity & Systems Analysis (SIGRITY/SYSANLS) 2021.1 HF3リリースが Cadence Downloads サイトからダウンロード可能となりました…

• 2 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , Sigrity , japanese blog , Clarity 3D Solver

PCB解析／ICパッケージ解析

System Analysis Knowledge Bytes: Clarity 3D Workbenchとは？

System Analysis Knowledge Bytesブログシリーズでは、Cadence®が提供するシステム解析ツールの機能と可能性について説明しています…

• 1 min read
Sigrity and Systems Analysis , system analysis , Sigrity , japanese blog , Clarity 3D Solver

Breakfast Bytes

Sunday Brunch Video for 7th November 2021

https://youtu.be/rfVN6CA6LjQ Made in Pacifica (camera Carey Guo) Monday: Designing…

• less than a min read
sunday brunch

Breakfast Bytes

IEDM Preview 2021

The big event for semiconductor process news is IEDM, the International Electron…

• 3 min read
iedm 2021 , IEDM

Breakfast Bytes

Semiconductor Numbers Everyone Should Know

I wrote a post a couple of years ago Numbers Everyone Should Know . It was about…

• 6 min read
capex , future horizons , malcolm penn , Semiconductor

Computational Fluid Dynamics

A New Era of Sustainable Ecotourism Through Design Optimization of Whale Watching…

Author: Nic de Waal, Managing Director,Teknicraft Design Based in New Zealand on…

• 3 min read
CFD , naval archicture , Marine Engineering , marine , Computational Fluid Dynamics , fluid dynamics , CFD Applications , simulation software , Omnis , naval

中文技术专区

Cadence Palladium Z2企业级硬件仿真平台荣获全球电子成就奖

2021 年 11 月 3 日，由全球电子技术领域知名媒体集团 ASPENCORE 举办的“ASPENCORE 全球高科技领袖论坛 - 全球双峰会”在深圳隆重举行…

FormerMember • less than a min read
dynamic duo , ACE award , palladium z2
CDNS - Fix Layout Hompage