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Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging

Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant
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Blog - Post List
Latest blogs

Verification

Why 10BASE-T1S Automotive Ethernet SoC Verification Needs More Than Simulation?

Cadence Multi-Platform Verification improves functional coverage and verification…

• 5 min read
Verification IP , Emulation , simulation

Computational Fluid Dynamics

How Fidelity CFD Improves Hydraulic Turbine Performance Prediction

Francis-99 Hydraulic Turbine (Trivedi, 2026) Accurately predicting the performance…

• 5 min read
Fidelity Charles Solver , CFD , turbomachinery , Hydraulic Turbines , Fidelity Turbo , Francis Turbine

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant

Artificial Intelligence (AI)

You'll Still Do the Work—You Just Won't Do the Boring Part

Agentic AI is about to change your flow. Here's what actually shifts—and why the…

• 5 min read
artificial intelligence , featured , agentic ai , NVIDIA , AI for design

Verification

Understanding PCIe 6.0 Power States: L0p vs L0s vs L1

PCI Express has always focused on a single goal: maximizing performance while minimizing…

• 5 min read
Verification IP , PCIExpress , PCIe 6.0

Corporate News

How Cadence and TSMC Are Accelerating AI Silicon Design at Advanced Nodes

Designing AI silicon for increasing AI/HPC workloads at advanced nodes has become…

• 5 min read
Advanced Node , TSMC Certified design flows , AI silicon

Physical Systems Simulation (CAE)

Everything to Look Forward to in Actran 2026.1

Cadence has released Actran 2026.1 , and this version adds more capabilities to two…

• 2 min read
Actran , Acoustic Simulation , PSDA , simulation software , NVH , FEA , CAE Software

System, PCB, & Package Design 

High-Speed Heterogeneous Integration with Multiphysics Analysis for TSMC SoW-X

2.5D advanced packaging is becoming increasingly critical as the demand for AI and…

• 2 min read
ucie , Sigrity X , SoW-X , Advanced IC packaging , Power Integrity , Signal Integrity , Clarity 3D Solver , PowerSI , multiphysics

Verification

From Pacemakers to ADAS: Verifying Systems Before Tapeout

Imagine discovering a critical bug in a heart pacemaker, not after deployment, not…

• 6 min read
Automotive , Protium , Palladium , medical , robotics , verification

Verification

DFI 6.0 Key Highlights of the Latest DFI Specification

The DDR PHY Interface (DFI) protocol specifies the signals, timing parameters, and…

• 4 min read
Verification IP , memory controller , PHY , VIP , hbm4 , DFI , DRAM , DFI 5.2 , DFI 6.0 , memory models , Lpddr6

Computational Fluid Dynamics

Fidelity Fine Marine for Faster, Smarter Marine Design Decisions

Marine design engineers and naval architects increasingly rely on computational fluid…

• 5 min read
CFD , marine applications , FINE Marine , Fidelity CFD , simulation software

Verification

UALink Under the Hood: Why Full-Stack Verification Wins

Inside the UALink stack: How 640 bytes travel from intent to wire, and why full-stack…

• 5 min read
Verification IP , UAL , verification strategy , System Design and Verification , VIP , UALink , verification

Cloud

When Infrastructure Becomes the Bottleneck in Chip Design

How Cadence OnCloud Managed Service Is Rewriting the Rules for Chip Design As chip…

• 7 min read
Cadence Managed Cloud , OnCloud Marketplace , cadence cloud , cloud eda

Digital Design

Boost Design Productivity by Cadence Digital Tools: Webinar Recording Available!

This webinar series delivers practical methodologies and tool insights to help digital…

• 2 min read
Cadence Online Support , webinar , Digital Implementation

Verification

NVMe 2.0 Explained: What’s New and Why It Matters

Non-Volatile Memory Express (NVMe) has become the dominant protocol for high-performance…

• 5 min read
NVMe 2.0 , Verification IP , non-volatile memory , NVM Express , NVMe , Non-Volatile Memory Express , VIP , Zoned Namespaces , NVMe Verification IP , NVMe specification , ZNS

System, PCB, & Package Design 

BoardSurfers: Installation Know-How: Cadence Licensing Floating vs. Single User

In PCB design teams today, the way licenses are managed can have a direct impact…

• 3 min read
OrCAD X Capture , Installation Know-How , cadence , license , SUL , PCB design , OrCAD X Presto , OrCAD X , installation , OrCAD X PCB Layout

Digital Design

Mastering Advanced Debug in Conformal LEC: Mapping to AI Driven Abort Resolution

This blogs provides a structured learning approach to Conformal LEC debug that combines…

• 2 min read
conformal lec , Equivalence Checking , cadence learning and support

Verification

Understanding USB4 Retimers and Their Role in Gen2 and Gen3 - Link Training

USB4 systems rely on retimers to enable reliable high-speed communication across…

• 5 min read
USB4 VIP , usb4 , retimers

Artificial Intelligence (AI)

The Feedback Loop Is the Moat

Every verification and design team I talk to is building agents right now. The demos…

• 14 min read
featured , AI in chip design , GenAI , AI/ML
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