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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Latest blogs

Corporate News

3D-IC in AI, HPC, and 5G: Bandwidth, Latency, and Energy per Bit Advantages

3D-IC technology is rapidly becoming the backbone of next-generation compute systems…

• 5 min read
Celsius Thermal Solver , Adavanced Packaging , Allegro X AI , Integrity 3D-IC Platform , AI-Driven Design , HPC , 3D-IC Technology , bandwidth , latency , Clarity 3D Solver , Energy per Bit

Verification

Don’t Let Bugs Slip Through Your RTL Design!

To validate your RTL design, are you still relying solely on simulation? Is there…

• 2 min read
FPV , Formal Analysis , formal , SoC , Jasper Apps , SVA , assertions , simulation , Formal verification

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured , CES , USB , interface IP , eUSB2 , AI PC

System, PCB, & Package Design 

Integrity 3D-IC Course Updated for Version 25.1

Unlocking Advanced 3D-IC Design: The Updated Integrity 3D-IC Course The semiconductor…

• 1 min read
3D-IC , package design , Integrity System Planner , Signal Integrity , interposer

Digital Design

Test Smarter, Not Harder: Explore Cadence’s Hands-On DFT Training Journey

In today's competitive semiconductor industry, robust testing methodologies are essential…

• 7 min read
DFT , Modus DFT , Genus Synthesis Solution , ATPG

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Two New Courses to Refine Your PI Skills

The System Analysis Knowledge Bytes blog series explores the capabilities and potential…

• 3 min read
Topology Workbench , Power Integrity , OptimizePI , Signal Integrity , Thermal Analysis , Celsius PowerDC

Verification

Virtualization, Collaboration, and Software at SDV Europe

The SDV Europe conference took place in Berlin (Germany) last week. It was a meeting…

• 6 min read
Automotive , virtual platforms , software-defined vehi , software development

System, PCB, & Package Design 

System Analysis Knowledge Bytes: NEW COURSE - PDN and Voltage Ripple Analysis

The System Analysis Knowledge Bytes blog series explores the capabilities and potential…

• 3 min read
Sigrity and Systems Analysis , Sigrity X , Topology Workbench , Power Integrity , OptimizePI , Signal Integrity , PDN Analysis

Verification

What's New in PSS 3.0? Key Additions to the Portable Stimulus Standard

The Portable Stimulus Standard (PSS) Language Reference Manual (LRM) has evolved…

• 6 min read
SoC verification , Perspec , SoC , pss

Analog/Custom Design

Virtuoso Studio: Navigating Smarter - Introducing the Virtuoso Dashboard

The Virtuoso Dashboard brings a unified, streamlined way to manage every window and…

• 4 min read
Virtuoso Studio , Custom IC Design

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured , CES , USB , interface IP , eUSB2 , AI PC

Analog/Custom Design

Virtuoso Studio: Stay Notified, Stay Productive-Introducing Notification Display

The latest update to Virtuoso Studio introduces a smarter, more seamless way to stay…

• 3 min read
Virtuoso Studio , Custom IC Design

Analog/Custom Design

Demystifying Standard Cell Characterization with Cadence Liberate

In the constantly evolving field of semiconductor design, accuracy and performance…

• 3 min read
Standard cell design , Standard Cell , nldm , characterization , library characterization , Custom IC Design , ECSM

System, PCB, & Package Design 

Revolutionizing Design: Cadence Community Forums Empowering AI-Driven Innovation

As AI-driven design gains momentum, Cadence is leading the way, leveraging agentic…

• 1 min read
MSA , TECHNICAL FORUMS , PCB design , Allegro PCB Editor

Corporate News

Thermal Management in 3D-IC: Modeling Hotspots, Materials, & Cooling Strategies

As three-dimensional integrated circuit ( 3D-IC ) technology becomes the architectural…

• 7 min read
Celsius Thermal Solver , Allegro X AI , Voltus IC Power Integrity , Integrity 3D-IC Platform , advanced packaging , 3D-IC Technology

Computational Fluid Dynamics

Significance of the High Lift Prediction Workshop for the CFD Community

The HLPW initiative continues to shape the path forward for more reliable, consistent…

• 3 min read
CFD , Aerospace , Meshing , Fidelity Pointwise , high-lift prediction

System, PCB, & Package Design 

IC Packagers: Optimizing Connectivity Between Die Escape Routing and BGA Balls

Package designers need to add escape routes to a die to facilitate further package…

• 4 min read
breakout routing , connection optimization , Allegro X Advanced Package Designer , escape routing , ISP , IC Packagers , Integrity System Planner , PCB design , allegro x , Allegro

Verification

Smarter Chips, Faster Checks: GravityXR Leading the XR Verification Shift

As XR technology accelerates, complexity rises—but speed to market remains the ultimate…

• 2 min read
performance , AVIP , GravityXR , virtual platforms , cadence , debug , Palladium , hybrid , Emulation , XR , testbench , verification

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

• less than a min read
news story , Verification IP , featured
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