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Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Computational Fluid Dynamics

Last Week at Fidelity CFD

While a large contingent of Fidelity CFD team members are at the AIAA SciTech Forum…

• 2 min read
CFD , turbomachinery , Computational Fluid Dynamics , fluid dynamics , T-Rex meshing , Fidelity CFD , Aerospace Engineering , cadencelive , Mesh Generation , Conferences

Breakfast Bytes

Design Enablement of 2D/3D Thermal Analysis and 3-Die Stack

At CadenceLIVE Europe back in November, one of the presentations was by Mohamed Naeim…

• 4 min read
3DIC , imec , CadenceLive Europe , cadencelive , thermal

Computational Fluid Dynamics

5 Small Features for Easy Meshing in Fidelity Pointwise

The big powerful features such as unstructured quadrilateral surface meshing, unstructured…

• 2 min read
CFD , Meshing Monday , Cell count , Small Features , engineering , simulation software , Mesh Generation , Cadence CFD , Fidelity Pointwise

Breakfast Bytes

Sunday Brunch Video for 22nd January 2023

https://youtu.be/ARCzcdPvLZg Made at Castle Rock State Park (camera Carey) Previous…

• less than a min read
sunday brunch

Breakfast Bytes

ST's Experience with Cadence Cerebrus

At CadenceLIVE Europe back in Thanksgiving week, one of the presentations was by…

• 3 min read
cerebrus , CadenceLive Europe , cadencelive , stmicroelectronics

Corporate News

AMD Is Designing Their EPYC Server Processors with the Dynamic Duo

AMD are known for creating some of the world’s most advanced processors. AMD’s EPYC…

• 1 min read
designed with cadence

Breakfast Bytes

Malcolm Penn: “We Are Stoking Capacity Just When We Don’t Need It”

On Tuesday this week, Malcolm Penn of Future Horizons gave one of the three annual…

• 4 min read
future horizons , featured , malcolm penn

Analog/Custom Design

Start Your Engines: Running Post-Layout Mixed-Signal Simulations with a More Complex…

Cadence ®︎  Spectre ®︎  With the DSPF-in-the-middle feature, designers can easily…

• 2 min read
AMS , AMS Designer , Start Your Engines , DSPF , Mixed-Signal , AMS simulation , Custom IC Design

SoC and IP

FMEDA-Driven SoC Design of Safety-Critical Semiconductors

Written by Francesco Lertora and Robert Schweiger 1.1 Introduction The growing…

• 8 min read
Safety Solution , Genus , functional safety , Midas Safety Platform , featured , Xcelium Safety , Jasper FSV , Verisium Manager Safety , USF , Automotive Option , Safety Analysis , Innovus , FMEDA , ISO 26262 , Virtuoso Assembler , Unified Safety Format , Safety Verification , Safety Compliance , Legato Reliability , Safety-aware Implementation

Verification

What Makes a Next-Generation Debug Solution?

For the past few decades, design and verification technology have made great progress…

• 5 min read
Functional Verification , debugging tips , debugging

Analog/Custom Design

Spectre Tech Tips: Dynamically Changing Spectre X Solver Settings

Spectre APS supports dynamically changing errpreset or reltol during a transient…

• 3 min read
Circuit simulation , spectre x , SPICE

Verification

Improve Regression Throughput and Find Bugs at Pace

Scaling chip size and increasing functionality over SoCs has increased complexity…

• 4 min read
xcelium simulator , Xcelium ML A

Breakfast Bytes

Improving RISC-V Processor Quality with Verification Standards and Advanced Meth…

At the RISC-V Summit in December, there were presentations halfway between a keynote…

• 4 min read
risc-v , Imperas , verification

Verification

Automating Data Coherency and Performance Testing of High-Speed SoCs with CXL In…

2023 is here, and technology trends around Compute Express Link (CXL) and the next…

• 2 min read

Digital Design

Training Insights - What's Your Weekend Plan? How About an Interactive Tour of the…

Well, we know you are busy, but it's time to develop your expertise in the synthesis…

• 3 min read
digital badge , Genus , training bytes , Synthesis , online training , Online Support

Digital Design

Training Insights – Webinar – Transforming your Timing Signoff Experience with Tempus…

This blog post describes the latest innovations in the Cadence®︎ Tempus™︎ Timing…

• 2 min read
Digital Implementation , Tempus Timing Signoff Solution , cadence learning and support

Breakfast Bytes

DesignCon 2023 Preview

Coming up at the end of this month is DesignCon, obviously not to be confused with…

• 3 min read
ben gu , DesignCon , designcon 2023

Computational Fluid Dynamics

Why Use T-Rex Hybrid Meshing?

As a CFD practitioner, have you experienced difficulty generating meshes in regions…

• 4 min read
CFD , surface meshing , Pointwise , T-Rex meshing , Fidelity CFD , engineering , simulation software , Mesh Generation , hybrid meshing

Verification

USB3 Gen T Tunneling Over USB4

USB Promoter Group recently released USB4 Version 2.0 and this updated specification…

• 2 min read
CDNS - Fix Layout Hompage