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Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Photonics: Riding the Waves

Coming up on January 11th is our annual photonics event. This year it is called CadenceCONNECT…

• 4 min read
Lumerical , silicon photonics , photonics

Analog/Custom Design

Virtuosity: Annotating Scalar Outputs for Single-Point Simulation in Virtuoso Visualization…

Can scalar outputs for single-point simulation be annotated in the graph window of…

• 3 min read
annotation , Scalar Outputs Annotation , ADE Explorer , Summary Label , Virtuoso Visualization and Analysis XL , Virtuoso Analog Design Environment , ViVA , Virtuosity , Single Point Simulation , ISR26 , Scalar Ouputs , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler

System, PCB, & Package Design 

Ascent: Training Insights: Controlling Design Versions in Allegro System Capture

The Version Control feature in Allegro® System Capture lets you track every modification…

• 4 min read
PCB , System Capture , 17.4 , 17.4-2019 , Training Insights , Allegro System Capture , ASCENT , Allegro

Life at Cadence

EV Maritime Is Creating Better Boats for a Better World

EV Maritime is a New Zealand-based marine technology business, decarbonizing the…

• 1 min read
CFD , designed with cadence

Breakfast Bytes

RISC-V Summit 2022

The RISC-V Summit took place in December. It was in person and virtual. Clearly,…

• 3 min read
risc-v , risc-v summit , walden international , risc-v foundation , Qualcomm , calista redmond

Life at Cadence

Words and Their Impact on Diversity, Equity, and Inclusion

An employee's perspective about diversity, equity, and inclusion: The Words Matter…

• 4 min read
Insights on Culture , inclusion , Technical Communications , GPTW , my life at cadence , WomenAtCadence , diversity , returnship , wordsmatterinitiative , inclusivelanguage , equity

Breakfast Bytes

CES 2023 Preview: Come and See Us in the Venetian

It's nearly a New Year, and as usual, CES (what used to be called the Consumer Electronics…

• 3 min read
Consumer Electronics Show , tensilica dsp , CES , Tensilica

Analog/Custom Design

Knowledge Booster Training Bytes - How to Model Analog Blocks with Verilog-AMS Wreal…

Do you know you can speed up analog or mixed-signal simulations with digital mixed…

• 9 min read
real number modeling , AMS , AMS Designer , training , DMS , training bytes , Spectre , RNM , AMS simulation , xcelium , Modeling , wreal , Custom IC Design , wreal Model , AMS Verification , vams

Breakfast Bytes

Using Clarity 3D Solver to Analyze 3D Packaging

3D packaging is becoming an increasingly popular solution for protecting and packaging…

• 3 min read
system-in-package , 3dhi , 3DIC , clarity

Digital Design

Knowledge Booster Training Bytes - In-Design Pegasus Signoff Verify Design (SVD)

In-Design Pegasus Signoff Verify Design (SVD) integrates Pegasus Signoff and Pegasus…

• 5 min read
Pegasus Verification System , pegasus , DRC , training bytes , Innovus , signoff , silicon signoff , RAKs , verification

Computational Fluid Dynamics

Last Week at Fidelity CFD

The year 2022 may be coming to an end, but Cadence Fidelity CFD never stops. Here…

• 3 min read
CFD , Pointwise , Computational Fluid Dynamics , adaptation , Mesh Generation

Life at Cadence

Intelligent System Design Ecosystem Development Is More Important than Ever

Electronic Design Automation (EDA) companies have long concentrated on ecosystem…

• 3 min read
ecosystem , intelligent system design

Digital Design

Training Insights - What Is IR drop? Is it Possible to Run IR-drop Analysis Using…

IR drop is the difference between two endpoints of the conducting wire during a current…

• 3 min read
rail analysis , Power Signoff , current density , Power Integrity , Cadence Online Support , training , Logic Design , training bytes , Digital Implementation , Innovus , Power Analysis , IR drop , power

Breakfast Bytes

ChatGPT: "A New Technology Adjusts Your Thinking About Computing"

Do you know what ChatGPT is? There's a good chance that the answer is "no" because…

• 6 min read
copilot , chatgpt , openai

Computational Fluid Dynamics

Play by the Rules – Identify and Fix Mesh Quality Issues Right Away!

The physical models, the solver algorithm, the grid type, the available computer…

• 4 min read
CFD , Meshing Monday , Mesh metrics , Commands , mesh quality , engineering , simulation software , Cadence CFD , Fidelity Pointwise

Analog/Custom Design

Virtuoso Meets Maxwell: Are You Telling Me I Can Auto-Generate a Package Schematic…

Yes, you heard that right! You can now auto-generate a package schematic from a package…

• 4 min read
IC Packaging , Footprint , VRF , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso MultiTech , Package Design in Virtuoso , Virtuoso , RF design

Breakfast Bytes

Sunday Brunch Video for 11th December 2022

https://youtu.be/6urbyyIDtZg Made at Koi Palace Contempo (camera Carey) Monday:…

• less than a min read
sunday brunch

Breakfast Bytes

Berlin Technik Museum and the Zuse Z1

The Berlin Technical Museum, officially the Deutsches Technik Museum, has a big collection…

• 4 min read
zuse , computer museums , berlin , museums

カスタムIC／ミックスシグナル

Virtuosity: カスタムIC設計フロー／手法―ポストレイアウト回路シミュレーションとGDSII生成

カスタム／ミックスドシグナル設計における現在の課題は、高速でシリコン精度の高い手法を持つことです。このブログ・シリーズでは、カスタムICの設計フローと手法の段階についてご紹介します…

• 1 min read
post-layout simulation , Analog Design Environment , Cadence blogs , ADE Explorer , DSPF , Virtuoso Analog Design Environment , Spectre , ICADVM20.1 , japanese blog , Custom IC Design , IC6.1.8 , ADE Assembler
CDNS - Fix Layout Hompage