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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

SoC and IP

Redefining SoC Design: The Shift to Secure Chiplet-Based Architectures

The semiconductor industry is undergoing a paradigm shift from monolithic system…

• 5 min read
security , Automotive , chiplets , physical ai , SoC

Corporate News

Cadence Launches Cache-Coherent HiFi 5s SMP for Next-Gen Audio Applications

Next-generation consumer and automotive audio is becoming increasingly sophisticated…

• 4 min read
news story , featured , Symmetric Multiprocessing , audio , Silicon Solutions , HiFi , Front Page Press Release , SMP , Tensilica , SSG , Xtensa

Verification

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium , Palladium , xcelium , VDE , helium , System Verification

RF Engineering

Empowering RF Power: Must-See Video Series for AWR Users!

Calling all AWR Microwave and RF designers—getting the most out of your tools just…

• 1 min read
RF , RF Simulation , analog/RF , Cadence Academic Network , AWR Design Environment , Virtuoso RF , Electromagnetic analysis , Analyst 3D FEM EM Simulator , RF design , AWR Microwave Office , AXIEM 3D Planar Simulator , microwave office , Visual System Simulator (VSS)

System, PCB, & Package Design 

Cadence Customers Share Experiences with Revolutionary PCB Design Methodology

PCB design teams are often caught in a repetitive cycle of design and simulation…

• 3 min read
Automotive , si/pi , Sigrity X Aurora , MIPI , PCB design , ADAS , allegro x

Academic Network

Accelerating Innovation: The SolarCar at Virginia Tech Team

At a time when sustainability and innovation are beautifully coming together, the…

• 2 min read
featured , Cadence Academic Network , CFD Simulations , Solar Car

SoC and IP

Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos

As we move through 2025, the momentum generated by Cadence continues to energize…

• 2 min read
Design IP , PCIe 7.0 , PCIe , PCI-SIG

Learning and Support

Analog and Digital IC Design Flows: The Past, Present, and Future of Electronics

Curious to see how your IC design skills (Analog/Digital) stack up—or where to level…

• 8 min read
college grads , digital design , blended training , AIML , specifications , xcellium , Custom IC flow , onboarding , Genus , Analog IC Flow , schematic design , GDSII , chip design , Tempus , pegasus , ASIC flow , RTL , video , Self Learning , tutorial , 3DIC , Cadence Online Support , APR , Digital IC Flow , Virtuoso ADE , place and route , Cadence training , digital badges , learninggap , training bytes , Virtuoso , Design and Verification , Semiconductor , Spectre , learnfast , Post Layout , Digital Implementation , GenAI , Innovus , physical design , Layout design , mobile , Virtuoso Layout , learning and support , Pre Layout , Verisium Manager , Quantus , online training , simulation , silicon , Digital Physical Design , Tape-out

Digital Design

Elevate Your EDA Skills: Achieve Unmatched PPA with Genus Synthesis Solution

As the electronic design automation (EDA) landscape continues to evolve, the importance…

• 4 min read
training , training bytes , Optimize , Genus Synthesis Solution , Synthesis , online training

System, PCB, & Package Design 

Discover Cadence Community Forums Resources for Tcl Scripting

In the world of PCB design and IC packaging, automation is key to enhancing productivity…

• 2 min read
PCB , Allegro X AI , cadence , awr , Tcl Scripting , Cadence Community Forums , community forum , SPB , PCB design

Corporate News

Driving the Future of High-Speed Computing with PCIe 7.0 Innovation

Escalating compute processing demands from generative and agentic AI applications…

• 4 min read
controller IP , Verification IP , featured , agentic ai , PHY , PCIe 7.0 , PCIe , HPC , high-performance computing , PCI-SIG

Digital Design

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus , Digital Implementation , AI

Cadence Japan

ケイデンスのエージェント型AIがSoC/システム・エンジニアリングの時間を数ヶ月短縮

最新のSoC設計の複雑さに対応するにあたり、AIを活用したチップ設計は必要不可欠となっています。設計に活用するエージェント型AIの段階、ケイデンスの関連製品などについては…

• less than a min read
news story , SoC , japanese blog , AI

SoC and IP

Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding

In our previous blog, we discussed the fundamentals of time-of-flight (ToF) technology…

• 5 min read
IP , vision processing , IoT , Tensilica DSPs , ip cores , Vision DSPs , Tensilica , vision , semiconductor IP , imaging , image processing

Verification

Insights from the Verification Software Track at CadenceLIVE Silicon Valley 2025

Earlier this month, I had the opportunity to attend CadenceLIVE Silicon Valley 2025…

• 2 min read
Verification IP , SVG , software , cadencelive , SimAI , xcelium , verification

Life at Cadence

Cadence Giving Foundation Awards 25 First-Generation Scholarships

Congratulations to the recipients of the 2025-2026 Cadence First-Generation Student…

• 1 min read
Cadence Giving Foundation , First-Generation Student Scholarships , LifeAtCadence

Learning and Support

Cadence Training at CadenceLIVE Silicon Valley 2025

CadenceLIVE Silicon Valley 2025, recently held at the Santa Clara Convention Center…

• 1 min read
agentic ai , Customer Training , Cadence ASK , cadencelive

SoC and IP

Arm Zena CSS – Accelerating Chiplet-Based SoC Design for AI-Defined Vehicles

Cadence is collaborating with Arm on their groundbreaking first-generation compute…

• 6 min read
virtual prototyping , ucie , featured , chiplet , virtual platform , CSA , compute subsystem , SDV , css , ARM , helium , AI

Corporate News

Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems

Design solution enables early software development, SoC design, and chiplet interoperability…

• 3 min read
Automotive , featured , ARM , compute subsystems
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