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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

PCB、IC封装：设计与仿真分析

详解PCB 设计中的功能性分区

本文要点： 为什么在 PCB 设计中需要使用功能性分区 设置功能性分区时的注意事项 利用 PCB 设计工具的功能和特性来创建分区 在PCB的设计中，往往采用了分区原理…

• less than a min read
Chinese blog , 走线 , 协同设计 , 设计分区 , symphony team design , PCB设计 , 中文 , Allegro

PCB、IC封装：设计与仿真分析

2021年度网课 I PCB系统设计——从原理图到投产

连接器不匹配、板间信号连接错误、设计需求传递失误…… 此类问题的发生，会导致设计前后端返工，严重影响产品上市时间，造成人力物力损失，这是项目团队及设计工程师最不希望发生的事情…

• less than a min read
System Capture , Chinese blog , 系统设计 , PCB设计 , 中文 , 直播网课 , online training , Allegro

PCB、IC封装：设计与仿真分析

升级到Allegro 17.4的10大理由

工欲善其事，必先利其器！ 为何不能错过Cadence Allegro 17.4 ？十大理由告诉你。 更加自动化的超实用功能助力打通智能电子设计任督二脉。 1. 整合前后端走线规则管理器…

• less than a min read
Chinese blog , 17.4 , allegro 17.4 , PCB设计 , 中文 , Allegro , 产品升级

PCB、IC封装：设计与仿真分析

六层PCB的漏斗设计

电气工程师尼古拉·特斯拉（Nikola Tesla）曾声称自己发明了一种带电粒子束投影仪——或者用科幻术语来说——离子炮（ion cannon）。这是一种防御性武器…

• less than a min read
PCB , Chinese blog , 柔性电路 , PCB设计 , 中文 , 多层电路 , Allegro

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster Training Bytes - Part 7: The Virtuoso ADE…

This blog shows how to efficiently use the Virtuoso ADE Assembler and Virtuoso ADE…

• 4 min read
blended , ADE Explorer , Explorer , training , Cadence training , digital badges , training bytes , Virtuoso , Analog IC Design videos , Cadence certified , Virtuoso Video Diary , Custom IC Design , online training , Custom IC , Assembler , ADE Assembler

Computational Fluid Dynamics

This Week in CFD

It's Friday which means it's time for that weekly roundup of news from the CFD world…

• less than a min read
CFD , Pointwise , fine/marine , Computational Fluid Dynamics , NUMECA , Mesh Generation , Meshing

Computational Fluid Dynamics

Hello, CFD Meshing World!

For the third time*, I find myself writing the obligatory, "Hello, World!" first…

• 2 min read
CFD , Pointwise , Computational Fluid Dynamics , NUMECA , Mesh Generation , Meshing

Digital Design

What’s Inside the GUI-Based Timing Report in Genus? Want to Explore?

Timing closure is one of the most crucial steps of a digital design. Therefore, to…

• 1 min read
report , Genus , gui , timing debug , Timing Optimization , debug report , Synthesis

Breakfast Bytes

Sunday Brunch Video for 2nd May 2021

https://youtu.be/1HEd6JCriCQ Made in Groveland CA (camera Carey Guo) Monday: Package…

• less than a min read
sunday brunch

System, PCB, & Package Design 

IC Packagers: Analyze, Simulate, and Resolve Signal Integrity Issues Using In-Design…

In today's ever-shrinking IC Package design cycles, it is almost imperative that…

• 3 min read
IDA , IC Packaging and SiP , IC Packagers , Allegro Package Designer , 17.4-2019 , PCB design

中文技术专区

向SiP过渡，EDA大有可为！

芯片设计可谓是人类历史上最细微也是最宏大的工程。它要求把上千亿的晶体管集成到不到指甲盖大小的面积上，这其中 EDA 工具的作用不可或缺。它于芯片设计就如同编辑文档需要的…

• less than a min read
SiP , chiplet , 系统级封装 , thermal

Breakfast Bytes

Offtopic: Miniatur Wunderland

Tomorrow and Monday are Cadence Global Holidays. Of course, May 1 is a holiday anyway…

• 4 min read
offtopic

Verification

What Disruptive Changes to Expect from PCI Express Gen 6.0

PCIe (Peripheral Component Interconnect Express) has long been the backbone of complex…

• 3 min read
SoC verification , Functional Verification , Modeling , verification

Breakfast Bytes

Arm V9A

Yesterday, I wrote about rapid adoption kits (RAKs) for the latest Arm server-class…

• 4 min read
isa , arm v9 , ARM

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: ICパッケージングプロセスのためのダイとBGAパッケージ間の接続の作成

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
IC , package , Footprint , Virtuoso Meets Maxwell , Virtuoso RF Solution , Package Design in Virtuoso , Allegro Package Designer Plus , BGA , die , OrbitIO , SiP Layout Option , ICADVM20.1 , japanese blog , Ball , Custom IC , bump

Breakfast Bytes

Rapid Adoption of the Arm Server-Class Processors

Arm has been moving from its foundational base in mobile into the data center, with…

• 3 min read
featured post , neoverse-v1 , neoverse , verification suite , digital full flow , neoverse-n2 , ARM

System, PCB, & Package Design 

ASCENT: Finding the Right Parts with Unified Search

Some people say that finding the right components for a design is the most time-consuming…

• 4 min read
System Capture , 17.4 , cadence , Dashboard , Search , logical design , LIVE BOM , logic capture , 17.4-2019 , PCB design , Allegro System Capture , Unified Search , New part request , ASCENT , BOM , Schematic , Allegro

Analog/Custom Design

Spectre Tech Tips: Introducing Electrothermal Simulation

Understanding the thermal performance of integrated circuits has been essential to…

• 3 min read
Electrothermal simulation , Spectre , Custom IC Design , Legato Reliability

Computational Fluid Dynamics

Thermal Analysis of a Hardware Blade System

Here's a video titled Thermal Analysis of a Hardware Blade System. The "blade system…

• less than a min read
CFD , celsius , protium x1
CDNS - Fix Layout Hompage