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New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
cdns - all_blogs_categories

Blog - Post List

Latest blogs

カスタムIC／ミックスシグナル

Start Your Engines: SimVision Mixed-Signal Debug Optionを使ってル・マンで優勝する

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• less than a min read
AMS Designer , Start Your Engines , simvision , analog/mixed-signal , Virtuoso , AMSD Flex Mode , japanese blog , mixed-signal design , debugging , mixed-signal verification

Computational Fluid Dynamics

Resolving Boundary Layers with Unstructured Quad and Hex Meshing: On-Demand Webi…

All things being equal, CFD practitioners prefer to use hexahedral mesh cells in…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics

Breakfast Bytes

The First Commercial Computer Shipped 70 Years Ago Today

Today is the 70th anniversary of a very significant event in all our lives, even…

• 5 min read
first computer , univac

System, PCB, & Package Design 

(P)SpiceItUp: Generating ISO 7637-2 Standard Pulse 2a in PSpice A/D

Many times, you would have required to create a standard pulse waveform that can…

• 2 min read
17.4 , OrCAD Capture , PSpiceA/D , Capture CIS , (P)SpiceItUp , 17.4-2019 , OrCAD

Digital Design

Library Characterization Tidbits: Define Measurements to Suit Your Characterization…

Do you have a requirement to specify measurements that are not default while performing…

• 3 min read
memory characterization , define_measure , Liberate MX , Library Characterization Tidbit , Liberate Characterization Portfolio

定制IC芯片设计

Virtuoso Meets Maxwell：为什么没有提到引线键合IC？

当今的许多模拟，RF和混合信号设计都要求在同一模组内部集成多个不同工艺的IC，以实现所需的性能目标。设计师使用异构器件集成方法能够获得单片IC (SoC) 设计上不容易达到的结果…

• 1 min read
Chinese blog , ICADVM18.1 , Co-Design , Virtuoso System Design Environment , Virtuoso RF Solution , Wirebond , Electromagnetic analysis , Virtuoso , Custom IC Design , Allegro

Breakfast Bytes

Intel IDM 2.0

You've probably read in the press that Intel's new CEO, Pat Gelsinger, laid out his…

• 6 min read
Intel , icf , idm 2.0 , intel custom foundry , foundry

Analog/Custom Design

Spectre Tech Tips: Detecting Leakage Path Current Hotspots

In circuit design, wrong connectivity may cause undesired leakage paths that may…

• 2 min read
Dynamic design checks , Spectre design checks , leakage path detection , Spectre , dyn_dcpath , dyn_subcktpwr

Digital Design

Pegasus: Get Your Wings: Virtuoso/Pegasus In-Design Signoff

The beauty of Pegasus is that it doesn’t only work excellently in standalone mode…

• 2 min read
Pegasus Verification System , Interactive SignOff Fill , pegasus , Pegasus Interactive , Density analysis , design for manufacturing

Breakfast Bytes

Stopping Online Fraud

I attended a webcast on Anti-Fraud organized by the RSA Conference in the leadup…

• 6 min read
security , ransomware , rsa

Analog/Custom Design

Virtuoso Video Diary: Tabular Graph in Virtuoso Visualization and Analysis XL

Do you know you can now use Tabular Graph feature in Virtuoso Visualization and Analysis…

• 2 min read
Analog Design Environment , ViVa-XL , custom/analog , ADE Explorer , Analog Simulation , ADE , Virtuoso , ViVA , Virtuosity , Custom IC Design , ADE Assembler

Academic Network

Cadence on YouTube

One of the most popular platforms of the whole Internet is undeniably YouTube ; this…

• 3 min read
Cadence Academic Network , academia , YouTube

Breakfast Bytes

Best of CadenceLIVE 2020: Hyperscale Data Centers

There is something in philosophy known as the Sorites paradox. If you have a heap…

• 4 min read
hyperscale , cadencelive , digital full flow , ARM

Life at Cadence

Women’s History Month Reflections with Alessandra Costa

Women’s History Month looks at the achievements women have made over the years. It…

• 3 min read
inclusion , Culture , cadence , WomeninTech , women , Women's History Month , diversity

RF /マイクロ波設計

[4月9日開催] CadenceTECHTALK 5G/6Gのシステム解析を加速する AWRと3D Glass Solutions

ケイデンスでは、これまで定期的にオンラインセミナーを開催し、高周波設計向けソリューションを紹介して参りました。今回は、5Gや今後の6Gのような無線通信に向けた取り組みとして独自の加工技術により注目されている3D…

• less than a min read
5G , RF , AWR Design Environment , awr , Analyst 3D FEM EM Simulator , japanese blog , 6G

Breakfast Bytes

National Security Commission on Artificial Intelligence

The (U.S.) National Security Commission on Artificial Intelligence recently published…

• 6 min read
artificial intelligence , uscai , microelectronics , AI

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: EMX — 業界をリードするRFIC用電磁界ソルバー

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
RFIC , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF Solution , Electromagnetic analysis , EMX , ICADVM20.1 , japanese blog , Custom IC Design

Verification

TileLink: Chip-Scale Cache-Coherent Interconnect Protocol

RISC-V, an open specification of an Instruction Set Architecture (ISA), which was…

• 1 min read
TileLink , Verification IP , risc-v , VIP , cache coherency

System, PCB, & Package Design 

IC Packagers: How to Quickly Push Design Connectivity across a Design

The task of IC/package co-design causes multiple challenges during the design cycle…

• 4 min read
17.4 , IC Packaging and SiP , IC Packagers , Allegro Package Designer , 17.4-2019 , PCB design
CDNS - Fix Layout Hompage