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Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Life at Cadence

DEI@Cadence: Spotlighting Cadence Veterans and Their Transitions to Tech

Diversity, equity, and inclusion (DEI) are not just words but values that are exemplified…

• 3 min read
Veterans Day , featured , Corporate Culture , DEI , veterans , DEIatCadence

Corporate News

Spirent Is Bringing Chipset Testing to Pre-Silicon Verification with Cadence

Spirent is a global provider of automated testing and assurance solutions for networks…

• 1 min read
prototyping , Protium , Palladium , designed with cadence , Spirent , Emulation , verification

PCB、IC封装：设计与仿真分析

Allegro X——新一代智能系统设计平台

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“ Allegro X, the Design Platform…

• less than a min read
PCB , Chinese blog , Allegro 23.1 , 原理图设计 , 机器学习 , 布线 , 系统设计 , 数据管理 , PCB 机器学习 , PCB设计 , Layout , 中文 , Allegro X 23.1 , 智能设计 , allegro x , 混合云 , X AI , Allegro

System, PCB, & Package Design 

Knowledge Bytes - Interposer Multi-Block Analysis Using Clarity 3D Layout

This post talks about the new Interposer Multi-Block Analysis flow that makes it…

• 3 min read
Clarity 3D Layout , Cadence Online Support , RAK , Gds2Spd Translator , interposer

Corporate News

When Excitement STEMs from Action

One hot August day in Tempe, Arizona, my wife LeAnn and I were sitting with our younger…

• 8 min read
inclusion , STEM , National STEM Day , giving back , women , diversity , women in tech , volunteer , Women in Technology

SoC and IP

UCIe Interoperability Between Intel and Cadence

Intel and Cadence are collaborating on an initiative to demonstrate interoperability…

• 3 min read
ucie , chiplets , IP integration , semiconductor IP , Design IP and Verification IP

Digital Design

How AI-Based Cadence Cerebrus Improves Performance and Reduces Area for TI

Microcontrollers (MCUs) have become the backbone of embedded designs and are fueling…

• 5 min read
cerebrus , PPA Improvement , Cadence Cerebrus

Corporate News

The Secret Life of Chip Engineers!

Chip engineers, the unsung heroes of the tech world, lead a secret life at work that…

• 2 min read
CNBC , featured , Generative AI , Jim Cramer , Squawk on the Street , GenAI

Analog/Custom Design

Stacked MOSFETs in Analog Layout

Below 28nm, maximum device length limitations mean that analog designers often need…

• 4 min read

Corporate News

Bringing Semiconductor Tapeouts to Engineering Education

Cadence’s PDK for SkyWater 130nm Open-Source Semiconductor Process Empowers Students…

• 4 min read
Cadence Academic Network , Education Kit , SKY130 , SkyWater Technology Foundry , Process Design Kit

System, PCB, & Package Design 

BoardSurfers: Training Insights—New OrCAD X Presto Layout Design Application

The OrCAD X Presto next-generation layout design environment within the OrCAD X platform…

• 2 min read
digital badge , Allegro X PCB Editor , BoardSurfers , 3dx , SPB23.1-2023 , PCB design and layout , Training Insights , OrCAD X Presto , OrCAD X , 23.1 , online training

Data Center

A Quick Start Guide: Building a Data Center Digital Twin

Even if you know a new software solution could help improve your workflow and data…

• 3 min read
data center , digital twin

System, PCB, & Package Design 

Cadence OrCAD X and Allegro X 23.1 is Now Available

The OrCAD X and Allegro X 23.1 release is now available at Cadence Downloads . This…

• 7 min read
TopXp , OrCAD X Capture CIS , Cadence Design Systems , padstack editor , Sigrity Aurora , featured , Allegro X PCB Editor , 3dx , PSpiceA/D , Allegro X Advanced Package Designer , APD , Cadence Doc Assistant , CDA , Topology Explorer , PCB design , OrCAD X Presto , OrCAD X , 23.1 , allegro x , Allegro X System Capture

SoC and IP

Cadence is a Contributing UCIe Consortium Member

This blog was originally posted on uciexpress.org . The Cadence member spotlight…

• 5 min read
ucie , chiplets , Design IP and Verification IP

Computational Fluid Dynamics

Don’t Miss the Amazing Ride that is McLaren Racing Fandom!

Hey there racing enthusiasts! Today I want to take a moment to talk about a partnership…

• 4 min read
CFD , artificial intelligence , F1 , featured , Computational Fluid Dynamics , formula one , McLaren Racing , mclaren , formula 1 , AI

Computational Fluid Dynamics

Cadence CFD Technology Update – Turbomachinery Workflow

The Cadence Fidelity Flow for Turbomachinery is a unique toolset that encompasses…

• 5 min read
CFD , turbomachinery , Cadence Fidelity Flow , simulation software , solvers , technology update , CadenceCONNECT CFD

Verification

USB4 Version 2.0 – Link Configurations

USB4 Version 2.0 specification was released by the USB Promoter Group earlier this…

• 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2 , usb4 router

Data Center

Validate Data Center Cooling Systems Externally Using CFD

It’s no secret that data centers are power hungry, so much so that data centers account…

• 4 min read
CFD , data center , cooling

Verification

Accelerate Your Debug with Verisium - Cadence's Next-Generation Debug Solution

Debugging low-power designs is its own unique challenge in the verification field…

• 3 min read
Low Power , Functional Verification , Verisium Debug , VerisiumDebug
CDNS - Fix Layout Hompage