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Featured

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
Corporate 2 Oct 2025 • 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
Corporate 1 Oct 2025 • 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
Vinod Khera 28 Sep 2025 • 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 25 Sep 2025 • 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
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Blog - Post List

Latest blogs

Breakfast Bytes

CDNLive: Ericsson Paving the Way for 5G

At CDNLive EMEA in Munich this week, there were two keynotes. The first was by Tom…

Paul McLellan 5 May 2016 • 3 min read
5G , CDNLive EMEA , Ericsson

Breakfast Bytes

DAC: One Month and Counting

It is May already and just a month until DAC. I am sure that you already know that…

Paul McLellan 4 May 2016 • 3 min read
dac2016 , DAC , Austin , dac53 , Design Automation Conference , 53dac

Whiteboard Wednesdays

Whiteboard Wednesdays—New Tensilica Vision P6 DSP

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the new Tensilica…

References4U 3 May 2016 • less than a min read
DSP , Whiteboard Wednesdays , IP , Chris Rowen , Vision P6 , Tensilica , convolutional neural networks , CNN

Breakfast Bytes

Embedded Vision: The Road Ahead for Neural Networks and Five Likely Surprises

It is the Embedded Vision Summit. Every year this event gets bigger, reflecting the…

Paul McLellan 3 May 2016 • 3 min read
Low Power , Rowen , Embedded Vision Summit , Vision P6 , tensilica vision p6 , Tensilica , convolutional neural nets , high performance , neural nets , Breakfast Bytes

Breakfast Bytes

New Algorithms for Vision Require a New Processor

Vision is everywhere. If you look at the number of sensors that are shipped, then…

Paul McLellan 2 May 2016 • 3 min read
recognition , tensilica vision p6 , Tensilica , vision , convolutional neural networks , neural networks , CNN

Breakfast Bytes

NVIDIA: Ten Months of Emulation on Palladium, Hours to Bring-Up

NVIDIA just released their next-generation GPU architecture called Pascal and a brand…

Paul McLellan 29 Apr 2016 • 2 min read
palladium z1 , NVIDIA , Palladium , Palladium XP , Emulation , Breakfast Bytes

SoC and IP

Cadence and Hardent demonstrate high resolution display interface for Automotive

At Cadence we aim to enable our customers’ need to reduce their own design time and…

Steve Brown 28 Apr 2016 • 1 min read
Hardent , Design IP , MIPI Alliance , CDNLive , DIP , MIPI , DSI , DSC

SoC and IP

High Speed East-West Interconnect at the Open Server Summit

This year’s Open Server Summit served up plates full of data…if it wasn’t obvious…

Steve Brown 28 Apr 2016 • 1 min read
PCIe Gen4 , 10G-KR , SerDes

Breakfast Bytes

EDPS Cyber Security Workshop: "Don't Let Convenience Trump Security"

EDPS, the Electronic Design Process Symposium, always has the second of the two days…

Paul McLellan 28 Apr 2016 • 4 min read
security , Monterey , chris eagle , EDPS , cyber security , naval postgraduate school , Breakfast Bytes

Breakfast Bytes

FD-SOI: Can I Design It and Manufacture It?

Yesterday I covered the analysis by ARM and VLSI Research on FD-SOI from the symposium…

Paul McLellan 27 Apr 2016 • 4 min read
28 FD-SOI , Samsung , VSLI Research , GlobalFoundries , ARM , FD-SOI

SoC and IP

CDNLive Silicon Valley 2016—The Bigger IP Picture

When a presentation makes us think about an industry on a whole new level and rethink…

Steve Brown 26 Apr 2016 • 1 min read
CDNLive , ip cores , Design IP and Verification IP

Whiteboard Wednesdays

Whiteboard Wednesdays - Floating-Point Core of Tensilica Vision P5 DSP

In this week's Whiteboard Wednesdays video, Dennis Crespo explains the optional vector…

References4U 26 Apr 2016 • less than a min read
Whiteboard Wednesdays , IP , Computer Vision , Tensilica , imaging , floating point , Tensilica Vision P5 DSP

Analog/Custom Design

Virtuoso Video Diary: Flexible Connectivity Support of Dummy Devices

Virtuoso Video Diary is envisaged to be an online journal that will relay information…

Rishu Misri Jaggi 26 Apr 2016 • 3 min read
dummy backannotation , Physical placement and layout , backannotation , Layout , Virtuoso , dummy abutment , dummy instances , dummy instance backannotation , dummy devices , dummy instance abutment , Virtuoso Layout Suite , dummies , VLS XL , custom design technology , Virtuoso Layout Suite XL , Abutment

Breakfast Bytes

FD-SOI: Is It Really a Thing?

Apparently, asking if something is really a thing is really a thing. So, recently…

Paul McLellan 26 Apr 2016 • 8 min read
FinFET , GlobalFoundries , ARM , FD-SOI

System, PCB, & Package Design 

What's Good About the Latest Constraint Manager? The 16.6-2015 Release has Several…

Significant enhancements to the 16.6-2015 Constraint Manager release have been made…

Jerry GenPart 25 Apr 2016 • 3 min read
PCB , SI , Allegro 16.6 , SigXP UI , Constraint Manager , Signal Integrity , Constraints , Grzenia

Analog/Custom Design

The Leader of the Orchestra: Getting Started with Virtuoso ADE Verifier

The members of an orchestra are often great virtuosi on their own instruments, but…

TeamADE 25 Apr 2016 • 3 min read
verifier , Virtuoso ADE Verifier , Virtuoso Analog Design Environment , Analog Design Environment

Breakfast Bytes

Patents and Standards, Managing the Challenge

One challenge with standards is the desire to avoid unknowingly incorporating patents…

Paul McLellan 25 Apr 2016 • 5 min read
vlsi technology , Rambus , ieee patent policy , GSM , loa , patent , IEEE-SA , IEEE , letter of assurance , Breakfast Bytes , standard

Breakfast Bytes

Andrew Kahng on PPAC Scaling Below 7nm

Last week Dr. Andrew Kahng came to town. He was at CDNLive, where his presentation…

Paul McLellan 22 Apr 2016 • 5 min read
ucsd , roadmap , ITRS , Cadence Academic Network , kahng , andrew kahng , 5nm , 7nm , power

Academic Network

Academic Track Makes Its Debut at CDNLive Silicon Valley

For the first time at CDNLive Silicon Valley, Cadence Academic Network hosted an…

susarla 21 Apr 2016 • 2 min read
Cadence Academic Network , CDNLive , academia
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