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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About the Latest in DEHDL? The 16.6-2015 Release Has Several New Enhancements…

The 16.6-2015 Design Entry HDL (DEHDL) release contains a few new capabilities! Read…

• 1 min read
Cadence Design Systems , hierarchy , Allegro 16.6 , DEHDL , Allegro Design Workbench , hierarchical schematics , SPB , Design Entry HDL , Design Entry , Grzenia , ConceptHDL

Life at Cadence

Cadence Recognized as a Best Workplace for Giving Back

I am so proud of the Cadence team. We were recognized by FORTUNE as #43 on their…

• 1 min read
Insights on Culture , Culture , Community , cadence , giving back , Fortune , GPTW , Tina Jones , Fortune 100 best companies to work for , great place to work

Breakfast Bytes

CDNLive: Design Technology Co-Optimization for N7 and N5

One of the challenges of developing a new node is that there are a lot of moving…

• 2 min read
n5 , Cadence Academic Network , CDNLive , lithography , CDNLive EMEA , imec , n7 , 5nm , 7nm , design of experiments , DTCO

Breakfast Bytes

Corporate Venture Capital for Semiconductor Start-Ups

A couple of weeks ago, Silicon Catalyst organized an evening panel about corporate…

• 5 min read
Intel , Applied Materials , cypress semiconductor , SanDisk , silicon catalyst , Qualcomm , corporate venture capital , wilson sonsini , corporate vc , Breakfast Bytes

Breakfast Bytes

CDNLive: Ericsson Paving the Way for 5G

At CDNLive EMEA in Munich this week, there were two keynotes. The first was by Tom…

• 3 min read
5G , CDNLive EMEA , Ericsson

Breakfast Bytes

DAC: One Month and Counting

It is May already and just a month until DAC. I am sure that you already know that…

• 3 min read
dac2016 , DAC , Austin , dac53 , Design Automation Conference , 53dac

Whiteboard Wednesdays

Whiteboard Wednesdays—New Tensilica Vision P6 DSP

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the new Tensilica…

• less than a min read
DSP , Whiteboard Wednesdays , IP , Chris Rowen , Vision P6 , Tensilica , convolutional neural networks , CNN

Breakfast Bytes

Embedded Vision: The Road Ahead for Neural Networks and Five Likely Surprises

It is the Embedded Vision Summit. Every year this event gets bigger, reflecting the…

• 3 min read
Low Power , Rowen , Embedded Vision Summit , Vision P6 , tensilica vision p6 , Tensilica , convolutional neural nets , high performance , neural nets , Breakfast Bytes

Breakfast Bytes

New Algorithms for Vision Require a New Processor

Vision is everywhere. If you look at the number of sensors that are shipped, then…

• 3 min read
recognition , tensilica vision p6 , Tensilica , vision , convolutional neural networks , neural networks , CNN

Breakfast Bytes

NVIDIA: Ten Months of Emulation on Palladium, Hours to Bring-Up

NVIDIA just released their next-generation GPU architecture called Pascal and a brand…

• 2 min read
palladium z1 , NVIDIA , Palladium , Palladium XP , Emulation , Breakfast Bytes

SoC and IP

Cadence and Hardent demonstrate high resolution display interface for Automotive

At Cadence we aim to enable our customers’ need to reduce their own design time and…

• 1 min read
Hardent , Design IP , MIPI Alliance , CDNLive , DIP , MIPI , DSI , DSC

SoC and IP

High Speed East-West Interconnect at the Open Server Summit

This year’s Open Server Summit served up plates full of data…if it wasn’t obvious…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes

Breakfast Bytes

EDPS Cyber Security Workshop: "Don't Let Convenience Trump Security"

EDPS, the Electronic Design Process Symposium, always has the second of the two days…

• 4 min read
security , Monterey , chris eagle , EDPS , cyber security , naval postgraduate school , Breakfast Bytes

Breakfast Bytes

FD-SOI: Can I Design It and Manufacture It?

Yesterday I covered the analysis by ARM and VLSI Research on FD-SOI from the symposium…

• 4 min read
28 FD-SOI , Samsung , VSLI Research , GlobalFoundries , ARM , FD-SOI

SoC and IP

CDNLive Silicon Valley 2016—The Bigger IP Picture

When a presentation makes us think about an industry on a whole new level and rethink…

• 1 min read
CDNLive , ip cores , Design IP and Verification IP

Whiteboard Wednesdays

Whiteboard Wednesdays - Floating-Point Core of Tensilica Vision P5 DSP

In this week's Whiteboard Wednesdays video, Dennis Crespo explains the optional vector…

• less than a min read
Whiteboard Wednesdays , IP , Computer Vision , Tensilica , imaging , floating point , Tensilica Vision P5 DSP

Analog/Custom Design

Virtuoso Video Diary: Flexible Connectivity Support of Dummy Devices

Virtuoso Video Diary is envisaged to be an online journal that will relay information…

• 3 min read
dummy backannotation , Physical placement and layout , backannotation , Layout , Virtuoso , dummy abutment , dummy instances , dummy instance backannotation , dummy devices , dummy instance abutment , Virtuoso Layout Suite , dummies , VLS XL , custom design technology , Virtuoso Layout Suite XL , Abutment

Breakfast Bytes

FD-SOI: Is It Really a Thing?

Apparently, asking if something is really a thing is really a thing. So, recently…

• 8 min read
FinFET , GlobalFoundries , ARM , FD-SOI

System, PCB, & Package Design 

What's Good About the Latest Constraint Manager? The 16.6-2015 Release has Several…

Significant enhancements to the 16.6-2015 Constraint Manager release have been made…

• 3 min read
PCB , SI , Allegro 16.6 , SigXP UI , Constraint Manager , Signal Integrity , Constraints , Grzenia
CDNS - Fix Layout Hompage