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Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P
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Blog - Post List
Latest blogs

Verification

Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Te…

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol…

• 3 min read
CXL , Verification IP , cadence , Functional Verification , VIP , PCIe , coherency , TripleCheck

Breakfast Bytes

HOT CHIPS: Arm's Morello

HOT CHIPS was back in the summer, and I covered it in two overview posts (and some…

• 5 min read
morello , hot chips , ARM , cheri , capability

System, PCB, & Package Design 

Enflame Unveils Lab-Correlated Design and Analysis Methodology for 2.5D HBM Desi…

At CadenceLIVE China 2022, AI-startup, Enflame Technology, revealed how their engineering…

• less than a min read
SI , PI , IC , SSN anlysis , IC Packaging , Sigrity XcitePI , Co-Analysis , Power Integrity , CadenceLIVE China , Advanced-IC Package design , silicon interposer , Signal Integrity , 2.5D HBM , cadencelive , Sigrity SystemSI , Clarity 3D Solver , simulation

Verification

CXL 3.0 Scales the Future Data Center

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and Gen…

• 4 min read
CXL , Verification IP , Memory , System Design and Verification , VIP , PCIe , Funcional Verification , coherency , PCIe 6.0 , AI , data centers , cloud computing , verification

Breakfast Bytes

CadenceLIVE Boston: State-of-the-Art Heterogeneous Integrated Packaging (SHIP)

Congress and the military love to come up with cute acronyms for programs, and so…

• 3 min read
RF , SiP , ship , ship-rf , 3dhi

Verification

Unraveling New Introduced PCIe 6.0 L0p

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

• 4 min read
Verification IP , VIP , PCIe , pcie gen6 , verification

Computational Fluid Dynamics

Streamline Reading and Writing Files from Fidelity Pointwise

For a CFD solution, a CAD geometry goes in and a CFD mesh comes out! Only if it was…

• 6 min read
Meshing Monday , geometry cleanup , Computational Fluid Dynamics , engineering , simulation software , Mesh Generation , Cadence CFD , Fidelity Pointwise

Verification

Unraveling PCIe 6.0 Training Sequences Update and Verification Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

• 4 min read
Verification IP , PCIe , pcie gen6 , verification

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Simplifying Signal and Power Integrity Analysis…

This System Analysis Knowledge Bytes blog describes how Sigrity Aurora can help simplify…

• 8 min read
IDA , Sigrity Aurora , Sigrity Topology Explorer , Power Integrity , SI/PI Analysis , Allegro Package Designer , Signal Integrity , PCB design , Clarity 3D Solver

Breakfast Bytes

Samsung Foundry Roadmap 2022

Recenty, it was the Samsung Foundry Forum (SFF). In fact, there was a pre-event for…

• 4 min read
Samsung , samsung foundry , samsung foundry forum , sff , safe

Computational Fluid Dynamics

Fidelity Pointwise 2022.1 Hot Fix 2 Now Available

Fidelity Pointwise 2022.1 Hot Fix 2 is now available for download and production…

• 1 min read
featured , Pointwise , Computational Fluid Dynamics , fluid dynamics , Mesh Generation , Meshing

Academic Network

Shift-Left Methodology for the Development of Hardware Accelerators Education Kit…

In order to describe the purpose of this education kit , let’s leave the EDA turf…

• 3 min read
virtual prototyping , featured , Education Kit , Tensilica , Stratus , SystemC , high level synthesis , helium

Life at Cadence

Hassle-Free Rigid-Flex PCB Bending EM Analysis

The functionality, safety, and effectiveness of devices using rigid-flex PCBs are…

• 4 min read
rigidflex , electromagnetic

Life at Cadence

Butterfly Network Puts Ultrasound on a Chip with Cadence

About two-thirds of the world’s population lacks access to medical imaging, whether…

• 1 min read
featured , designed with cadence , vision , butterfly network

Breakfast Bytes

2022 Kaufman Award Honors Giovanni De Micheli

This year's Kaufman Award honors Giovanni De Micheli, usually known as Nanni. Of…

• 5 min read
Kaufman Award , CEDA , IEEE , kaufman hall of fame , esd alliance

Verification

Unraveling PCIe 6.0 FLIT Mode Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

• 6 min read
Verification IP , featured , verification strategy , Functional Verification , VIP , PCIe , pcie gen6 , verification

Analog/Custom Design

Virtuoso ICADVM20.1 ISR28 and IC6.1.8 ISR28 Now Available

The ICADVM20.1 ISR28 and IC6.1.8 ISR28 production releases are now available for…

• 2 min read
Analog Design Environment , Cadence blogs , ADE Explorer , cadence , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Layout EXL , ICADVM20.1 , IC Release Blog , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

Verification

Importance of MDIO Interface for Ethernet.

M edia I ndependent I nterface M anagement ( MIIM ), or M anagement D ata I nput…

• 1 min read
Verification IP , uvm , SoC verification , IP verification , Ethernet VIP , Functional Verification , Cadence VIP portfolio , MDIO Interface , Ethernet

Life at Cadence

How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?

The chip design industry is going through exciting times. Process nodes with smaller…

• 5 min read
advanced process nodes , Genus Synthesis Solution , Innovus Implementation
CDNS - Fix Layout Hompage