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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Analog/Custom Design

Knowledge Booster Training Bytes - Switched Capacitor and C2V Converter-Based Ci…

In this Knowledge Booster blog, let us talk about the simulation of the circuits…

• 4 min read
blended , blended training , Spectre RF , learning , newton , training , digital badges , training bytes , Spectre , Cadence certified , Virtuoso Video Diary , Custom IC Design , online training , Custom IC

PCB、IC封装：设计与仿真分析

哪些原因会导致 BGA 串扰？

本文要点：• BGA 封装尺寸紧凑，引脚密度高。 • 在 BGA 封装中，由于焊球排列和错位而导致的信号串扰被称为 BGA 串扰。 • BGA 串扰取决于入侵者信号和受害者信号在球栅阵列中的位置…

• 1 min read
PCB , Chinese blog , IC封装设计 , Allegro Package Designer Plus , PCB设计 , 中文

Analog/Custom Design

Virtuoso Meets Maxwell: Custom Passive Device Authoring - Part 2 (LVS)

Welcome to the second blog on Custom Passive Device Authoring (CPDA). RF designers…

• 6 min read
EM simulation , Virtuoso Meets Maxwell , Virtuoso RF Solution , Electromagnetic Solver , Virtuoso Multi-Technology Solution , Custom IC Design , IC23.1

Artificial Intelligence (AI)

Are There Pitfalls to Embracing Generative AI in Chip Design?

With every new technology comes a learning curve, some are steeper than others, and…

• 6 min read

Digital Design

Training Webinar: IR-Aware ECO Optimization Using Voltus and Tempus Solutions

This blog post draws your attention towards an upcoming training webinar "IR-Aware…

• 1 min read
Static timing analysis , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Cadence training , Digital Implementation , Tempus Timing Signoff Solution , IR drop

Computational Fluid Dynamics

Meshing Complex Marine Geometries Has Never Been Easier!

The Cadence Fidelity CFD platform offers various meshing technologies for leading…

• 5 min read
CFD , webinars , marine , Fidelity CFD , engineering , simulation software , Mesh Generation , Cadence CFD

Cloud

Designing with Cadence…in the Cloud

Recogni builds the world’s highest-performing chips that are fully functional for…

• less than a min read
Managed Cloud , Cloud Passport , cloud , oncloud , cadence cloud , palladium and protium cloud

System, PCB, & Package Design 

IC Packagers: Transfer of IC Routing Blockage to Allegro X Advanced Package Designer…

A physical implementation designer may want to add a routing blockage on a chip or…

• 4 min read
Allegro X Advanced Package Designer , IC Routing , IC Packagers , Integrity System Planner , Allegro

Artificial Intelligence (AI)

Transformative Potential of Generative AI: Alleviating Talent Shortages and Diversifying…

In the previous posts in this series, we read about the transformative power of generative…

• 3 min read
featured , LLM

Artificial Intelligence (AI)

Keep Up with the Revolution—AI/ML Fundamentals Training

Want to learn what artificial intelligence and machine learning (AI/ML) are all about…

FormerMember • 1 min read
artificial intelligence , ml , machine learning , AI/ML , AI

PCB、IC封装：设计与仿真分析

信号反射和阻抗失配的联系

本文要点• 电路中或传输线上的阻抗失配会产生反射，回到信号源。• 当信号反射时，向末端负载传输的功率就会减少。• 阻抗匹配发挥了一种双重作用，即通过抑制反射使功率传输到负载…

• less than a min read
SI , Chinese blog , 仿真分析 , PSPICE , 中文 , 阻抗 , 信号完整性 , 信号反射

PCB、IC封装：设计与仿真分析

如何轻松完成刚柔结合 PCB 弯曲的电磁分析？

对于使用刚柔结合 PCB 的系统，确保功能性、安全性和有效性是重中之重，尤其是用于先进医疗植入物、高精度关键军事设备以及类似受监管机密设备的系统。为此，一定要对它们进行全面详尽的仿真…

• less than a min read
Chinese blog , EM分析 , PCB设计 , 电磁分析 , 中文 , 网格 , EM , Clarity 3D Solver , 刚柔结合

PCB、IC封装：设计与仿真分析

多层 PCB 的热应力分析

本文要点： 多层 PCB 有很多优点，但是，多层结构也会给电路板带来热应力问题。 热应力分析是一种温度和应力分析方法，用于确定多层 PCB 中的热应力点。 热应力分析结果有助于…

• 1 min read
PCB , Celsius Thermal Solver , 热 , Chinese blog , 多层PCB , 热分析 , 热应力 , 中文 , Sigrity , 热基础

Digital Design

Keep Up with the Revolution—Cadence Cerebrus Training

Can you imagine specifying your design goals and having a tool intelligently optimize…

FormerMember • less than a min read

Computational Fluid Dynamics

Cleaning Marine Geometries Has Never Been Easier!

Ship designers and naval architects increasingly use computational fluid dynamic…

• 4 min read
CFD , geometries , marine design , geometry cleanup , Fidelity CFD , engineering , simulation software , Cadence CFD , Meshing

PCB、IC封装：设计与仿真分析

面向 TSMC InFO 技术的高级自动布线功能

本文翻译自Cadence "Breakfast Bytes Blogs"专栏作者Paul McLellan文章"Advanced Auto-Routing for…

• 1 min read
IC , Chinese blog , 异构集成 , DHI-WLP , chiplet , 3DIC , 布线 , TSMC , IC封装设计 , 中文 , InFO

Analog/Custom Design

More Current Mirrors in Analog Layout

In my previous blog, ( Current Mirrors in Analog Layout ) I looked at a few techniques…

• 4 min read

カスタムIC／ミックスシグナル

Virtuoso Studio: 正しい意図を持ってコラボレートしよう！

当社の最新AI技術を活用したカスタムデザインソリューションであるVirtuoso Studioは、30年にわたる業界の知識とリーダーシップを活用し、革新的な機能や比類のない生産性を実現する再考されたインフラストラクチャおよびクラシックなデザイン境界を超える新しいレベルの統合プラットホームを提供します…

• less than a min read
collaboration , Virtuoso Studio , AMS Designer , Virtuoso , Layout design , japanese blog

Verification

Best Practices to Achieve the Highest Performance Using Xcelium Logic Simulator …

Xcelium Logic Simulator Profile Analysis Our previous post discussed measuring parameters…

• 4 min read
Xcelium Logic Simulator , profile analysis , xcelium simulator , xcelium , best practices , verification
CDNS - Fix Layout Hompage