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Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Latest blogs

Corporate News

Cadence and AVCC to Advance Physical AI Innovations for Autonomous Vehicles

Cadence has joined the Autonomous Vehicle Computing Consortium (AVCC) , marking a…

• 2 min read
Automotive , IP , featured , physical ai , chiplet , Safety , system on chip , HPC , high-performance computing , ADAS

Corporate News

Chip Design Industry Reaches an AI Inflection Point

The chip design landscape has hit a transformative milestone, one that signals a…

• 5 min read
inflection point , featured , agentic ai , agentic

Corporate News

Cadence Agentic AI Reduces SoC/System Engineering Time by Months

The modern design landscape is evolving rapidly, driven by shrinking design cycles…

• 5 min read
featured , agentic ai , AI

Corporate News

Transforming Chip Design with Agentic AI: Introducing Cadence Cerebrus AI Studio

The industry's first agentic AI, multi-block, multi-user SoC design platform To…

• 4 min read
featured , Cadence Cerebrus , Digital Implementation , AI

Analog/Custom Design

Virtuoso Studio IC23.1 ISR14 Now Available

Virtuoso Studio IC23.1 ISR14 production release is now available for download.

• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso , Custom IC Design , Custom IC , IC design , IC23.1

Verification

UALink: Powering the Future of AI Compute

On April 25, the UALink Consortium officially released the UALink 200G 1.0 Specification…

• 2 min read
Verification IP , VIP , Ethernet , PCIe , HPC , UALink , AI/ML

SoC and IP

Linux-Based Audio Platform with Cadence Tensilica HiFi 5

A Linux-based audio platform with Cadence Tensilica HiFi 5 enables rapid algorithm…

• 3 min read
hifi 5 , IP , Tensilica , HiFi 5s , HiFi Audio

System, PCB, & Package Design 

BoardSurfers: Training Insights: Advanced Design Verification with RAVEL

RAVEL, which stands for Relational Algebra Verification Expression Language, is designed…

• 5 min read
PCB , Allegro X PCB Editor , DRC , ravel , Allegro X Advanced Package Designer , APD , PCB Editor , Allegro Package Designer , PCB design , Constraints , allegro x

Computational Fluid Dynamics

Exploring Turbulence: An Introductory Approach

Key Points Turbulence is a widespread phenomenon that occurs across many scales…

• 5 min read
CFD , turbulence , LES

Digital Design

Semiconductors: Pioneering Extraordinary Growth in the 20th Century

Semiconductors have revolutionized the world, powering everything from smartphones…

• 3 min read
Static timing analysis , online courses , Cadence Online Support , RTL-to-GDSII , Joules , training bytes , Digital Implementation , Innovus , Synthesis , online training , physical implementation , cadence learning and support

SoC and IP

CadenceLIVE 2025: The Field Guide for Defense Digital Engineering

Modern microelectronics is a new operating theater for many in the Defense Industrial…

• 2 min read
cadencelive , defense

Digital Design

Microlearning: The Snackable Knowledge Training Videos

Are you looking to level up your digital design skills—one byte at a time? Ohoo!…

• 5 min read
DFT , RTL2GDSII Flow , online courses , Functional Verification , Gate level simualtion , LEC , STA , Cadence training , training bytes , Digital Implementation , implementation , physical design , Synthesis , RTL design , RTL2GDSII Webinar

System, PCB, & Package Design 

System Analysis Knowledge Bytes - Optimizing LPDDR5X Performance with Sigrity X

This blog post explores the capabilities of Cadence Sigrity X Advanced SI in designing…

• 5 min read
Sigrity and Systems Analysis , TopXp , PBA , DDR interface , Sigrity X , system analysis , measurement , license , SPB , ddrx , lpddr5x , Sigrity , High Speed design , simulation , Advanced SI

SoC and IP

Time-of-Flight Decoding with Tensilica Vision DSPs

Today, let's break down time-of-flight (ToF) and how Tensilica Vision DSPs can be…

• 1 min read
IP , Consumer Electronics , cadence , video , Tensilica DSPs , ip cores , Tensilica , vision , semiconductor IP , cadencelive , imaging , image processing

Verification

eMMC: The Embedded Storage Powering On-Device AI

In today's world of increasingly intelligent devices, efficient and reliable storage…

• 2 min read
Verification IP , VIP , verification

Verification

Using PSS Registers with Perspec for Portable Programming Sequences

When you use Cadence’s Perspec System Verifier and the Portable Test and Stimulus…

• 6 min read
Perspec , perspec system verifier , pss

Corporate News

Cadence to Power the Fourth Industrial Revolution in Collaboration with NVIDIA

The convergence of artificial intelligence (AI), robotics, and the internet of things…

• 1 min read
NVIDIA , Protium , Palladium , designed with cadence

SoC and IP

Cadence San Jose Hosts JEDEC LPDDR Task Group Meeting

Low-power DDR ( LPDDR ) SDRAM has been one of the most widely used memories in the…

• 2 min read
Verification IP , Design IP , IP , VIP , JEDEC , LPDDR PHY IP , DRAM , LPDDR Controller IP , Design IP and Verification IP , Lpddr6

Analog/Custom Design

Custom Analog IP Migration in Virtuoso Studio

Join Cadence Training and presenters from our CIC experts for this free technical…

• 3 min read
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