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Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Things You Didn't Know About Virtuoso: Which Way Should I "Go"?

Just a short post this week, as I've been quite busy recording videos for some of…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

DAC Virtual Platform Workshop

Back in early May, I wrote that it was Not Too Early to Start Thinking About DAC…

• 1 min read
DAC , virtual platform , embedded software , metric-driven verification

RF Engineering

Periodic Steady-State Analysis for DC-to-DC Converters

In " Spectre RF by any other name ...", a non-RF application for Spectre RF's periodic…

• 3 min read
DAC , shooting newton , Spectre RF , THD , DC-to-DC converters , RF design , pss , SFDR

Verification

Create a Sine Wave Generator Using SystemVerilog

Two capabilities in SystemVerilog allow for the creation of a module that can produce…

• 2 min read
SystemVerilog , AMS , Functional Verification , Incisive , Incisive Enterprise Simulator (IES) , IES , IES-XL

SoC and IP

DDR3 DRAMs Update in June 2009

Abstract: DDR3 DRAMs, after a long period of floundering about, wondering 'when they…

• 3 min read

Verification

Yikes - Synopsys is Following Me!

No, I'm not being paranoid -- Synopsys, my largest competitor, is literally following…

• 2 min read
Specman , Functional Verification , OVM , OVM e , Coverage-Driven Verification , CDV , e , Twitter , eRM

Verification

The Golden Age of Electronics

About a month ago I took my family to The Bakken Museum in Minneapolis, Minnesota…

• 4 min read
System Design and Verification , C-to-Silicon , PCI Express , ESL

Verification

Using Constraints to Pass Configuration Options in the Unit Hierarchy (Top-Down approach…

To allow for increased solvability, some constraints that were previously uni-directional…

• 4 min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , e , team specman , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , AOP , IES-XL

Analog/Custom Design

Optimization Environment Enables Effective Reuse of Existing Design Modules

In order to complete a brand new design on time, it is an important factor to effectively…

• 1 min read
virtuoso layout migrate , optimization , Virtuoso , reuse , Custom IC Design

Verification

Xilinx SoC FPGAs Ideal Fit For OVM and MDV

Processor-based FPGAs represent 40% of all the design starts today and will rise…

• 1 min read
SystemVerilog , Functional Verification , OVM , Incisive , xilinx , MDV , IES , FPGA

System, PCB, & Package Design 

What's Good About an FPGA Co-Design Environment? - Watch The Video For Answers

Check out Hemant Shah - Product Marketing Director for Allegro PCB Products - highlighting…

• 1 min read
FPGA: ASIC Prototype , FPGA System Planner , FSP , PCB design

Analog/Custom Design

Things You Didn't Know About Virtuoso: RMB, OMG! ;-)

I apologize for the Internet slang in the title ( urbandictionary calls OMG "the…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Digital Design

Cadence: Committed to DFM

On June 10, Cadence issued a press release that mentioned “…decreasing the level…

• 1 min read
Advanced Node , Mixed-Signal , encounter , Virtuoso , Manufacturability sign-off , Digital Implementation , DFM

SoC and IP

Unity's New CMOx Memory Technology Appears on Horizon

Summary: Unity Semiconductor has come forth recently with a new candidate for Storage…

• 7 min read

Verification

Send Us Suggestions for Updating the e/Specman Quick Reference Card

Team Specman is about to start a project to refresh the e /Specman Quick Reference…

• less than a min read
Specman , Tech Pubs , Functional Verification , e , team specman , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Speeding up SystemC compilation with Incisive SystemC

If you’re a C++ and SystemC programmer you know that when you’ve spent all day tracking…

• 6 min read
System Design and Verification , OSCI , embedded software , Incisive , SystemC analysis , George Frazier , System Design & Verification , SystemC , SystemC: OCSI , ESL

Digital Design

Technical Webinars Hosted by the Experts - Don't Miss Them!

Starting June 23, 2009, Cadence technical experts will host a series of technical…

• 1 min read
Low Power , webinars , advanced design , design planning , Digital Implementation , physical implementation , timing convergence

SoC and IP

Taiwan Agonistes: Why Taiwan Should Demote DRAMs, and Agressively Expand Its Foundry…

Taiwan Cannot Shake Attraction for DRAMs, Marches Down Same Path as Many Others Before…

• 13 min read

Verification

VCS Runs OVM -- 2 Years Late, But Welcome None the Less

Something seems to have changed in the Synopsys VCS simulator; the Web2.0 world is…

• 1 min read
SystemVerilog , OVM Professionals Network , Functional Verification , OVM , Incisive , PSL , IES , OVMWorld
CDNS - Fix Layout Hompage