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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Breakfast Bytes

HOT CHIPS: Esperanto's Dave Ditzel and 1000 Minions

At HOT CHIPS this morning, Dave Ditzel of Esperanto is presenting their latest chip…

• 5 min read
minion , risc-v , esperanto , maxion , hot chips

System, PCB, & Package Design 

IC Packagers: New Releases Are Full of New Stuff!

This marks our third and final look at the biggest new features in this major update…

• 6 min read
17.4 QIR3 , IC Packaging and SiP , APD , IC Packagers , Allegro Package Designer , 17.4-2019

中文技术专区

针对GPGPU设计，Cadence RTL到Signoff流程解密

近年来，随着GPU在通用计算领域的高速发展，逐渐将应用范围扩展到图形之外，例如人工智能、深度学习和自动驾驶。这些领域的特点要求GPU在并行处理海量数据的同时提供更高的访存速度和浮点运算能力…

FormerMember • less than a min read
Glitch power , GPGPU , OCV , 预测布局

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Signal, Power, and Thermal Integrity using Layout…

The System Analysis Knowledge Bytes blog series explores the capabilities and potential…

• 4 min read
Celsius Thermal Solver , Help Menu , OptimizePI , Sigrity , Clarity 3D Solver , Layout Workbench , XtractIM , PowerDC , Systems Analysis , PowerSI

Breakfast Bytes

CadenceLIVE: Xilinx's Thunder-Bus

At CadenceLIVE Americas in June, Raghukul presented on Thunder-Bus, a low-latency…

• 2 min read
protium x2 , Protium , xilinx

SoC and IP

PCIe for Automotive - DesignCon/DriveWorld 2021

DesignCon 2021, Drive World Conference, and Embedded Systems Conference are a joint…

• 3 min read
CXL , Design IP , IP , featured , PCIe Gen4 , ip cores , PCI , PCIe PHY

Academic Network

Academic and Entrepreneur Tracks at CadenceLIVE Europe 2021

CadenceLIVE Europe 2021 will be hosted on October 19th. This year will be a virtual…

• 2 min read
Entrepreneur , Cadence Academic Network , Master Thesis Award , cadencelive

Computational Fluid Dynamics

CFD, Cars, and Cadence - Two Events Next Week

The Cadence CFD team is excited about two automotive engineering events next week…

• 1 min read
CFD , Automotive , Pointwise , Computational Fluid Dynamics , CFD Applications , Mesh Generation , Omnis

Breakfast Bytes

Rowhammer: Beating DRAM into Submission

Way back in 2014, a DRAM vulnerability called Rowhammer was revealed. This is a silicon…

• 5 min read
security , ddr5 , Memory , DDR4 , JEDEC , DRAM , rowhammer

Life at Cadence

My Life at Cadence: Nick Phillips

People come to Cadence to have meaningful careers, work with some of the brightest…

• less than a min read
Insights on Culture , Culture , cadence , GPTW , my life at cadence , great place to work , cadence emea

Breakfast Bytes

Tensilica ConnX B10 in GF 22FDX for Automotive Grade 1

At CadenceLIVE Americas back in June, GlobalFoundries presented a case study on using…

• 4 min read
adaptive body bias , 22fdx , abb , gf , GlobalFoundries , FD-SOI

Breakfast Bytes

BlackHat: Hacking a Capsule Hotel—Ghost in the Bedrooms

Security conferences always seem to have at least one interesting presentation that…

• 6 min read
security , blackhat

System, PCB, & Package Design 

ASCENT: Accessing System Capture Functions Through a Browser-Based Dashboard

So, if you are an electronics design program manager or team manager, it’s unlikely…

• 2 min read
17.4-2019 , Allegro System Capture , ASCENT , 17.4-QIR3

Breakfast Bytes

Aerospace and Defense Day

At the end of July, Cadence had its CadenceCONNECT Aerospace and Defense Day. For…

• 4 min read
A&D , RF , celsius , 3D-IC , awr , Analysis , thermal , aerospace & defense , Custom IC , clarity

System, PCB, & Package Design 

IC Packagers: What Else Is There to Know About the New Release?

Last week we looked at new features largely targeting your manufacturing flow. Layer…

• 6 min read
17.4 QIR3 , IC Packaging and SiP , APD , IC Packagers , Allegro Package Designer , 17.4-2019

Computational Fluid Dynamics

This Week in CFD

A brief notice here that this Friday the 13th is also This Week in CFD day. Of note…

• less than a min read
CFD , Automotive , Pointwise , fine/marine , jobs , Computational Fluid Dynamics , CFD Applications , Mesh Generation

System, PCB, & Package Design 

BoardSurfers: Reasons to Move to 17.4-2019 Hotfix019 of Allegro PCB Editor

Cadence OrCAD and Allegro 17.4-2019 Hotfix 019 was rolled out in mid-July and is…

• 4 min read
PCB , Models , BoardSurfers , 3D Canvas , what's new , PCB Editor , Layout , 17.4-2019 , hotfix 019 , Allegro PCB Editor , microvia , 17.4-QIR3 , Allegro

System, PCB, & Package Design 

(P)SpiceItUp: Speed and Reliability Through Tried and Tested TI-PSpice Models

When time and quality are at a premium and you are in a hurry to meet a tight schedule…

• 4 min read
17.4 , Models , OrCAD Capture , PSpiceA/D , (P)SpiceItUp , 17.4-2019 , hotfix 019 , library , Allegro

PCB設計／ICパッケージ設計

(P)SpiceItUp: PSpice Part Searchを用いて、カテゴリ、概要、または機能 (Category, Description, or Function…

設計者としては、回路設計の初期段階での要件はまったく異なります。つまり、回路デザインを実装するときに必要な部品情報と、テストや解析のためにシミュレーションするときに必要な部品情報は性質が異なるのです…

• less than a min read
OrCAD Capture , PSpiceA/D , (P)SpiceItUp , PSPICE , 17.4-2019 , OrCAD , japanese blog
CDNS - Fix Layout Hompage