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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
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Blog - Post List

Latest blogs

RF /マイクロ波設計

μWaveRiders:最新の AWR Design Environment オプティマイザでゴールを決める

The Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題は、Cadence AWR…

• less than a min read
AWR Design Environment , Pointer-Hybrid optimizer , RF design , microwave office , global minima , japanese blog , Optimization cost , Optimizer goals , Optimizer methods

Verification

How to Verify Complex PIPE Interface Based PHY Designs?

High-end SOC architectures today requiring more area and higher speed to transfer…

• 2 min read

RF Engineering

μWaveRiders: Scoring Goals with the Latest AWR Design Environment Optimizer

AWR V22.1 software introduces the Pointer-Hybrid optimization method which uses a…

• 4 min read
featured , AWR Design Environment , Pointer-Hybrid optimizer , RF design , microwave office , global minima , Optimization cost , Optimizer goals , Optimizer methods

Breakfast Bytes

Sunday Brunch Video for 20th November 2022

https://youtu.be/gLQbSlICCaE Made in Munich Englischergarten (camera Carey) Monday…

• less than a min read
sunday brunch

System, PCB, & Package Design 

IC Packagers: Training Insights: What's New in the Allegro X Advanced Package Designer…

The Allegro X Advanced Package Designer course provides all the essential training…

• 3 min read
Allegro X Advanced Package Designer , 22.1 , IC Packagers , Training Insights , online training , Allegro

Verification

How Renesas Reduced Automotive SoC Verification Time

The automotive world is conquering new technological heights, piggybacking on advanced…

• 5 min read
Automotive , verification time , Renesas , customer success , Verisium Manager , vManager

Life at Cadence

Cardo Brings Cutting-Edge Audio Connectivity to Groups in Motion

Motorcyclists riding through extreme conditions need a communication device that…

• 1 min read
designed with cadence , Tensilica

Breakfast Bytes

Old Programming Languages

This is the last day before a break. Tomorrow I fly to Germany for CadenceLIVE Europe…

• 11 min read
offtopic

Breakfast Bytes

Software 2.0

I recently came across the idea of "software 2.0". I was watching a Lex Fridman interview…

• 5 min read
software 2.0 , neural networks , andrej karpathy , AI

Life at Cadence

Effective Measurement Is the Key to Meeting Environmental Sustainability Goals in…

Hyperscale compute, using high-performance connected processors, continually transforms…

• 2 min read
featured , data center , thermal

Breakfast Bytes

Passage: Wafer-Scale Programmable Photonic Communication

One of the most intriguing chips presented at HOT CHIPS earlier this summer was Lightmatter…

• 2 min read
lightmatter , silicon photonics , photonics , passage

Data Center

Cadence Enhances Data Center Digital Twins with NVIDIA Omniverse

Companies across all industries are beginning to harness the power of simulation…

• 2 min read
CFD , featured , data center

Life at Cadence

Mobilizing the Impact of Our "One Team" Culture

Since 2018, Cadence has partnered with Team4Tech to make a mark on the world by connecting…

• 5 min read
team4tech , Cadence Cares , LifeAtCadence

Computational Fluid Dynamics

Last Week at Fidelity CFD

Merry Monday, and welcome to another look back at what we've been up to at Fidelity…

• 3 min read
CFD , turbomachinery , turbulence , Cascade Technologies , CHT , Computational Fluid Dynamics , cadencelive , Mesh Generation , Meshing

Breakfast Bytes

Tensilica for Automotive Radar

At the recent Linley Fall Processor Conference, Cadence's David Bell presented Tailored…

• 2 min read
linley processor conference , ConnX , radar , Tensilica , Breakfast Bytes

System, PCB, & Package Design 

ASCENT: Synchronizing Schematic and Layout Designs

To successfully develop and maintain designs, you need some way to track changes…

• 3 min read
System Capture , 17.4 , schematic layout linking , Layout , 17.4-2019 , PCB design , netlist exchange , ASCENT , design synchronization , Schematic

Life at Cadence

Michigan Electric Boat Is Propelling the Naval Industry

The University of Michigan Electric Boat (UM-EB) is a student team that’s designing…

• 1 min read
CFD , FINE Marine , designed with cadence

Academic Network

Introducing DATE 2023 Young People Programme

The DATE conference , the biggest EDA conference in Europe will be held April 17…

• 4 min read
DATE , Career Fair , PhD Forum , Young People Programme

Breakfast Bytes

Linley: Enabling Heterogeneous Integration of Chiplets Through Advanced Packaging…

At the recent Linley Fall Processor Conference, the first day wrapped up with a presentation…

• 3 min read
packaging , linley processor conference , AMD , 3dhi , 3DIC , xilinx
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