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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

CFD（数値流体力学)

Illinois Blowerは流体シミュレーションによってファンの性能を44％改善

石油化学およびその他の産業では、空気の換気や500°C以上の有害な塩化物ガスの処理のためにファンを使用しています。これらのファンの最大運転回転速度は業界標準によって管理され…

• less than a min read
CFD , turbomachinery , fans , Computational Fluid Dynamics , fluid dynamics , simulation software , japanese blog , simulation

Computational Fluid Dynamics

Shortage of Chips a Challenge for Vehicle Electrification

Electric Vehicle (EV) market growth, along with the bourgeoning investments in autonomous…

• 5 min read
battery capacity , Automotive , gallium nitride , electric vehicles , intelligent manufacturing , chip production , Silicon chips , silicon carbide

Computational Fluid Dynamics

Illinois Blower Increases Fan Performance by 44% with Fluid Dynamics Simulation

Illinois Blower develops and builds custom centrifugal fans and blowers for a variety…

• 5 min read
CFD , turbomachinery , fans , Computational Fluid Dynamics , fluid dynamics , simulation software , simulation

Analog/Custom Design

Virtuoso ICADVM20.1 ISR24 and IC6.1.8 ISR24 Now Available

The ICADVM20.1 ISR24 and IC6.1.8 ISR24 production releases are now available for…

• 2 min read
Analog Design Environment , Cadence blogs , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Virtuoso RF , Layout EXL , Virtuoso Analog Design Environment , Virtuoso , ICADVM20.1 , IC Release Blog , Virtuoso ADE Explorer , Virtuoso Layout Suite , Custom IC , Virtuoso ADE Assembler , IC6.1.8

Breakfast Bytes

ESD Alliance CEO Outlook (and the Kaufman Dinner)

The ESD Alliance has two events coming up in the next couple of months, both of which…

• 2 min read
kaufman dinner , semi , ceo outlook , esd alliance

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: RF回路でのカスタム受動デバイス – デバイスかそれともインターコネクトか

'Virtuoso Meets Maxwell' はVirtuoso RF ソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
S-parameter , Extraction , Smart View , Layout versus schematic , pegusas , RFIC , parasitic , LVS , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic Solver , Electromagnetic analysis , EMX , Quantus Extraction Solution , graybox , ICADVM20.1 , japanese blog , blackbox , Quantus , Custom IC Design , EMX Solver , VMM

Computational Fluid Dynamics

CFD Wind Studies for Ship Superstructures

Besides resistance, seakeeping and propulsion, wind loads play an important role…

• 2 min read
CFD , naval archicture , Marine Engineering , shipping , marine , fine/marine , Wind Study , Computational Fluid Dynamics , fluid dynamics , IMO regulations , CFD Applications , simulation software , NUMECA , naval

Breakfast Bytes

The Framework Laptop and Right to Repair

You might have heard some discussion about "the right to repair" or R2R. Some of…

• 5 min read
framework laptop , right to repair , r2r

Verification

How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device?

DDR Memory is an important part of a wide array of electronic system designs in various…

• 2 min read
Verification IP , Industry Insights , Functional Verification , DFI 5.1 , VIP , SoC , DFI , storage , DFI Technical Group , memory models , DDR-PHY , DDR-PHY Interface

Analog/Custom Design

Virtuosity: Virtuoso-Innovus Interoperability — Making Trim Shapes Interoperable

Make your Virtuoso designs Innovus ready by ensuring trim and metal shapes follow…

• 4 min read
Analog Digital Designs , Mixed-Signal Designs , Trim Shapes , Virtuoso , Virtuoso Innovus Interoperability , Virtuosity , Innovus , ICADVM20.1 , leConvertTrimmedShapesToPRStyle , leReportTrimmedShapesInCustomStyle , Custom IC Design , Interoperable IC Designs , Virtuoso Layout Suite

Life at Cadence

AI Unleashes Chip Designer Productivity

EDA has a history of enabling breakthrough designer productivity. AI in EDA isn’t…

• 5 min read
cerebrus , ai-driven , digital , implementation

Breakfast Bytes

Cadence: Sustainable by Design

Last week, Cadence published the Cadence Sustainability Report 2021 (link at the…

• 5 min read
sustainability report 2021 , sustainability , power

Computational Fluid Dynamics

This Week in CFD #468

It's a sunny 81 degrees here in Fort Worth as I type this and after going outside…

• less than a min read
CFD , Computational Fluid Dynamics , fluid dynamics , Mesh Generation

Verification

Who Inspires You? - An SVG Women's History Month Spotlight

This month, we join millions celebrating and recognizing the achievements of women…

• 6 min read

Breakfast Bytes

March 2022 Update: Intel Video, India, Apple

Amazingly, it is already the last Friday in March (and so the last Friday in Q1,…

• 4 min read
Intel , Apple , transistor , m1 ultra , update , India

Learning and Support

What is IEEE 1500 Wrapper Insertion Flow in Genus Synthesis Solution

Are you searching for a scalable standard architecture for enabling test reuse and…

• 2 min read
digital badge , blended training , training bytes , Cadence certified , online training , Cadence Support Portal , Cadence support

Digital Design

Mitigating Congestion, CTS, OCV and Other Challenges using Cadence Tools and Sup…

With the shrinking gemoetries and data-intensive endeavours of the upcoming industries…

• 6 min read
debug , Routing , Unconstrained Path , congestion , OCV , SOCV , RAKs

Breakfast Bytes

DVCon: UVM Birds of a Feather

At the recent DVCon 2022, there was a UVM Birds of a Feather meeting. UVM stands…

• 5 min read

System, PCB, & Package Design 

BoardSurfers: Specifying Layer Information for Multi-Layer Rigid and Flex Stacku…

To manufacture a product that performs as you intended, it is imperative that you…

• 5 min read
APD+ , 17.4 , Signal Intregrity , BoardSurfers , layer stacks , Layout , 17.4-2019 , Allegro PCB Editor , Allegro
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