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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
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Blog - Post List

Latest blogs

Verification

The Best C++ Debugger is Not the Best SystemC Debugger

I mentioned in a previous article that I have two girls who are excellent debaters…

• 7 min read
virtual platforms , windows , TLM 2.0 , SystemC , Visual Studio , C++ , debugging

System, PCB, & Package Design 

What's Good About Allegro GRE Rake Functionality? You’ll Need the SPB16.3 Release…

The SPB16.3 Global Route Environment (GRE) Expanded Rakes functionality provides…

• 1 min read
PCB , SPB16.3 , global route , Routing , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , "PCB design" , PCB design , Allegro PCB Editor , GRE , Allegro

Digital Design

Five-Minute Tutorial: Encounter Command Line Help

Hi everyone, and welcome to the first Five-Minute Tutorial! I have several things…

• 2 min read
EDI system , tutorial , encounter , help , Digital Implementation , command line , five minute , five-minute

SoC and IP

What’s the best SSD for less than $150? Techspot publishes budget SSD roundup.

A year ago, Techspot.com tested and reviewed SSDs and the least expensive drive it…

• less than a min read

SoC and IP

SanDisk and NDS collaborate to add features and video on demand to set-top boxes…

NAND Flash vendor SanDisk and set-top box software vendor NDS Group Ltd are collaborating…

• less than a min read

Verification

All I Really Need to Know About MDV I Learned From Hollywood - Part 3

This is my third and final blog entry in a series using quotes from famous Hollywood…

• 3 min read
vPlan , verification planning , metric-driven verification , Hollywood , MDV , IP modeling , verification

Digital Design

Encounter 101: Implementing ECOs with ecoDesign

When people say "ECO" in the context of back-end digital implementation tools, they…

• 2 min read
ECO , encounter , Digital Implementation , ecoDesign

SoC and IP

Late Event Notice: The Makers of the Microchip: Creating the Planar Integrated Circuit…

You still have two weeks to sign up for an extremely interesting lecture titled …

• 1 min read

SoC and IP

IEEE Spectrum article provides more insight into HP/Hynix memristor pact

Despite some obvious technical flaws (DRAM cost/bit is not 10x less than NAND Flash…

• less than a min read

Digital Design

Encounter Puzzler Solution: Where Did My Fences Go?

A couple of days ago I posted a puzzler on a scenario where fences couldn't be seen…

• 3 min read
fences , Floorplanning , encounter , Digital Implementation , puzzler

SoC and IP

Pliant trades off firmware complexity against MLC NAND Flash capacity in enterprise…

The multiplicative storage capacity of MLC (multi-level cell) NAND Flash is a siren…

• 1 min read

SoC and IP

Samsung sees continuing strong demand for NAND Flash

Yesterday, I wrote that Samsung was sending caution messages about DRAM demand based…

• less than a min read

SoC and IP

Is the latest DRAM bobsled run already coming to an end? Samsung and Hynix say “Maybe…

The semiconductor business has been cyclic ever since it came into existence half…

• 1 min read

Verification

Tech Tip: Save Steps With Automatic Witness Checks

This is just a quick reminder that the "witness_check" define command has an option…

• less than a min read
ABV , Functional Verification , Formal Analysis , formal , IEV , IFV

SoC and IP

Icy Dock internal multi-drive bay crams four 2.5-inch drives (SATA or SAS) into 5…

OK, so this blog entry isn’t about memory so much as it’s about a cool ancillary…

• 1 min read

SoC and IP

Super Talent caches Flash memory on USB 3.0 drive with 32 Mbytes of DRAM, performance…

There’s been plenty of discussion about using NAND Flash memory to cache HDDs and…

• 1 min read

Digital Design

Encounter Puzzler: Where Did My Fences Go?

A while back I visited a customer I see on a fairly regular basis. As soon as I entered…

• 1 min read
fences , Floorplanning , encounter , Digital Implementation , puzzler

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Polygon Selection? Look at SPB16.3 and See!

The Allegro PCB Editor allows selection of items by several means. In preselect mode…

• 1 min read
polygon , PCB , SPB16.3 , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , PCB design , Allegro PCB Editor , PCB Capture , Allegro

SoC and IP

SD Association adds pins to SD card format to boost transfer rates to 300 Mbytes…

Hot on the heels of the rollout of high-speed SDHC and SDXC UHS-I cards that approach…

• less than a min read
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