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Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Artificial Intelligence (AI)

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design
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Blog - Post List
Latest blogs

PCB解析／ICパッケージ解析

Clarity 3Dソルバーをクラウドで実行

今朝、ケイデンスは Clarity 3D Solver Cloudを発表しました。ハイブリッドクラウド環境内で“Clarity 3D Solver”と“Cloud…

• 1 min read
Sigrity and Systems Analysis , ADE , cadence cloud , hybrid cloud , japanese blog , Clarity 3D Solver , clarity

PCB解析／ICパッケージ解析

Clarity 3D Transient Solverリリース - EMCコストの効果的な削減が可能に！

昨日、Paul Cunninghamが新製品System VIPを発表したことを、私の投稿 System VIP：Logistics for Cache-Coherent…

• less than a min read
Clarity 3D Transient Solver , electronmagnetic susceptibility , cloudburst , cadence cloud , japanese blog , clarity

Digital Design

Glitch?? Do Not Let It Impact Your Design Power!!

A glitch, although, is an unnecessary signal transition in your design. But its impact…

• 1 min read
Low Power , RTL , Joules , glitch , Power Analysis , power optimization

System, PCB, & Package Design 

IC Packagers: 17.4-2019 Hotfix 019 Is Here! What Does That Mean?

The HotFix 019 of our 17.4-2019 release is available for download and installation…

• 5 min read
17.4 , IC Packaging , degassing , APD , IC Packaging & SiP design , Allegro Package Designer , 17.4-2019 , ICPackagers , Allegro

Computational Fluid Dynamics

Big Wave Surfboard Optimization Using Cadence's Pointwise and CRUNCH CFD

Stephen Barr, Roger Birkbeck, Jeremy ShipmanCombustion Research and Flow Technology…

• 13 min read
CFD , Marine Engineering , Pointwise , Computational Fluid Dynamics , fluid dynamics , Mesh Generation

Computational Fluid Dynamics

What Is Intern Reading Club?

As the summer winds down, interns are busy completing their assigned projects and…

• 4 min read
Interns , internships , soft skills , workplace skills

Digital Design

Conformal Low Power Verification

Learn to verify low-power designs using Conformal ® Low-Power Verification. We've…

FormerMember • less than a min read

Computational Fluid Dynamics

Cadence CFD at the SU2 Conference 2021

Last month's SU2 Conference brought together the community of researchers and practitioners…

• 3 min read
CFD , Automotive , T-Rex , Aerospace , Pointwise , automation , Computational Fluid Dynamics , voxels , adaptation , Mesh Generation

定制IC芯片设计

Virtuoso Meets Maxwell: Virtuoso RF Solution快速入门

不同种类的模组设计之间的集成趋势引起了PCB 设计风格的流程正向IC设计风格的流程转变。对于任何一个先进的模组设计流程而言，多芯片封装的跨结构设计和验证都必不可少…

• 1 min read
Rapid Adoption Kit , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Layout EXL , Chinese blogs

Breakfast Bytes

Sunday Brunch Video for 8th August 2021

https://youtu.be/_dRTQm0DyG0 Made in New York City (camera Carey Guo) Monday: Intel…

• less than a min read
sunday brunch

Computational Fluid Dynamics

This Week in CFD

Welcome to the weekend. It's time for This Week in CFD , all the CFD news that I…

• less than a min read
CFD , Computational Fluid Dynamics , fluid dynamics , CFD Applications

カスタムIC／ミックスシグナル

Virtuosity: 分散型ファームにおけるリソースの最適な利用

読者の皆さん、こんにちは。 ジョブやシミュレーションを実行するために、どれくらいのリソースが必要なのか、誰しも疑問に思ったことがありますよね。これは難しい問題で…

• less than a min read
SGE , Analog Design Environment , LBS , Job Policy , ADE , LSF , Virtuoso , Virtuosity , distributed processing , japanese blog , Custom IC Design , IC6.1.8 , Assembler , ADE Assembler

Breakfast Bytes

Offtopic: Today You, Tomorrow Me

It is the last day before a break and so I write about whatever I feel like. It's…

• 7 min read
offtopic

System, PCB, & Package Design 

ASCENT: More Reasons to Move to 17.4-2019 Hotfix 019

Picking up from where we left off in the previous post , let’s look at some more…

• 4 min read
System Capture , 17.4 , publish for manufacturing , LIVE BOM , 17.4-2019 , Allegro Pulse , hotfix 019 , Allegro System Capture , PLM , web dashboard , ASCENT , Allegro

Breakfast Bytes

The Systems Designer's Guide to...Systems Analysis

There is a new book in the System Designer's Guide to... series, published by i.007e…

• 5 min read
featured post , system analysis , electrical analysis , Thermal Analysis

Breakfast Bytes

Intel's Process and Packaging Roadmaps

There are only three companies that are on the real leading edge. As you probably…

• 5 min read
Intel , intel 4 , featured post , intel 7 , emib , process roadmap , intel 3 , foveros , intel 20a

Breakfast Bytes

Sunday Brunch Video for 1st August 2021

https://youtu.be/I0AYf5V_irg Made in Long Ridge Open Space Preserve (camera Carey…

• less than a min read
sunday brunch

Computational Fluid Dynamics

This Week in CFD

It's a Global Recharge Day here at Cadence so why not get recharged by keeping up…

• 1 min read
CFD , Automotive , Computational Fluid Dynamics , CFD Vision 2030 , CFD Applications

Analog/Custom Design

Spectre Tech Tips: Spectre High Impedance Node Check Overview

Circuit checks enable you to analyze typical design problems, such as high impedance…

• 4 min read
spectre aps , dyn_floatdcpath , dyn_float_tran_stat , dyn_highz , highz , static_highz , Spectre , static checks , spectre x , Design Checks , floating node
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