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Featured

Corporate News

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
Corporate 18 Jun 2026 • 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
Corporate 16 Jun 2026 • 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
Corporate 15 Jun 2026 • 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
Corporate 11 Jun 2026 • 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

Verification

Advancing Digital Verification with Dynamic Duo III's Accelerated Computing

In an era where the complexity of chip design is accelerating at an unprecedented…

Reela Samuel 4 Jun 2024 • 5 min read

RF Engineering

Unlock Your RF Engineering Potential with a Cadence AWR Free Academic Trial!

Are you ready to revolutionize your RF design experience? Look no further! Cadence…

Jasmine 4 Jun 2024 • 2 min read
featured , Cadence Academic Network , AWR Design Environment , awr , TRIAL , AWR training , RF design

The India Circuit

Insight to Impact: My Volunteering Journey in Cambodia with Team4Tech

Introduction Volunteering has always been a passion of mine, and when the opportunity…

Asim Khan 3 Jun 2024 • 5 min read
CadenceCares , team4tech , cadence , volunteering

Analog/Custom Design

Virtuoso Studio IC23.1 ISR7 Now Available

Virtuoso Studio IC23.1 ISR7 production release is now available for download.

Virtuoso Release Team 3 Jun 2024 • 1 min read
Cadence blogs , Virtuoso Studio , IC Release Blog Announcement , Cadence Community , IC23.1

Analog/Custom Design

How Do You Ensure the Reliability of Your Design in Virtuoso Studio?

Designers have long recognized the need to analyze the reliability of ICs. Two commonly…

Niyati Singh 2 Jun 2024 • 3 min read
blended , blended training , relxpert , Reliability Report , learning , training , reliability options , Cadence training , digital badges , training bytes , Virtuoso , Cadence certified , Virtuoso Video Diary , reliability analysis , Custom IC Design , online training , Custom IC , reliability

Computational Fluid Dynamics

Are Wind Tunnels For an Eternity in Automotive Design Testing

Automotive design currently relies on computational fluid dynamics (CFD) simulations…

Veena Parthan 2 Jun 2024 • 6 min read
Automotive , GPU acceleration , wind tunnels , Millennium M1 , simulation software , LES , Aerodynamics , CFD supercomputer

Corporate News

Cadence to Accelerate AI and Scientific Computing in Collaboration with NVIDIA

In a rapidly evolving technological landscape, Cadence's collaboration with NVIDIA…

Corporate 31 May 2024 • 3 min read
featured , NVIDIA , accelerated compute , Anirudh Devgan , Scientific Computing , cadencelive , AI

Digital Design

Voltus Voice: Breaking Ground with Voltus-InsightAI—A Detailed Exploration

In the 2nd blog on Voltus InsightAI, we examine the intricate technologies that make…

Jonathan Zhang 30 May 2024 • 5 min read
artificial intelligence , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Innovus Implementation System , Generative AI , Power Integrity , Voltus InsightAI , Placement , EMIR

Life at Cadence

DEI@Cadence: Celebrating AAPI Heritage and Inclusion Through ERGs

Diversity, equity, and inclusion (DEI) are not just words but values that are exemplified…

Claire Ying 30 May 2024 • 6 min read
inclusion , DEIB , ERG , DEI , AAPI , diversity , DEIatCadence , great place to work

Data Center

Data Center Software: Power Management Functionality

Power availability is a key consideration within data center operations, especially…

Dave King 30 May 2024 • 3 min read
data center , digital twin , power management

Corporate News

The Sustainable Olympics: A Green Future in Global Sports

Sustainability is no longer a buzzword; it's an imperative. With increasing global…

Corporate 29 May 2024 • 5 min read
esg , sustainability , Olympics , 2024 Paris Olympics , technology

Life at Cadence

DEI@Cadence: An Experience For All at the Great Place to Work Summit

Diversity, equity, and inclusion (DEI) are not just words but values that are exemplified…

Ryan Robello 29 May 2024 • 4 min read
featured , Cadence Culture , GPTW , Corporate Culture , ERG , great place to work

Analog/Custom Design

Virtuoso Studio: Simplified Review of Operating Point Parameter Values

Read on to know about the Operating Point Parameters Summary window that gives you…

Gaurav Maindola 28 May 2024 • 2 min read
Analog Design Environment , Operating point summary window , Virtuoso Studio , Operating Point Information , Virtuoso Analog Design Environment , Custom IC Design , Virtuoso ADE Explorer , Virtuoso ADE Assembler , IC23.1

Computational Fluid Dynamics

Second Lap: The Comeback of Once-Banned F1 Technologies

The intriguing journey of Formula One (F1) technologies that were initially developed…

Veena Parthan 28 May 2024 • 5 min read
Automotive , Banned technologies , racing cars , formula one

カスタムIC/ミックスシグナル

Virtuoso Meets Maxwell: Virtuoso StudioがSiP DRC検証に革命を起こす

'Virtuoso Meets Maxwell'はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

Custom IC Japan 28 May 2024 • less than a min read
cross-fabric , SiP , DRC , Virtuoso Meets Maxwell , Package Design in Virtuoso , Virtuoso , japanese blog , Checks , Allegro

SoC and IP

Cadence San Jose Hosts JEDEC LPDDR (Low-Power DDR) Task Group Meeting

Low-power DDR (LPDDR ) SDRAM has been one of the most widely used memories in the…

Shyam Sharma 28 May 2024 • 1 min read
Verification IP , ddr5 , IP , JEDEC , HBM , GDDR , memory IP , DRAM , lpddr5 , lpddr5x , memory models

Digital Design

Forget the Wireloads! Gear Up for Physical Synthesis to Tackle PPA Results!

The traditional synthesis process relies on the Wireload models to estimate the delays…

Neha Joshi 27 May 2024 • 3 min read
digital badge , Genus , training bytes , physical design , Synthesis , online training , Online Support

System, PCB, & Package Design 

Podcast: PCB 3.0: More Power to the EEs

Today’s electrical engineers (EEs) are being asked to design increasingly complex…

NaomiM 23 May 2024 • less than a min read
PCB , electrical engineer , PCB design , Allegro

Corporate News

Longhorn Racing Is Building the Future of Electric Vehicles

Not only is Longhorn Racing, a student-run organization at the University of Texas…

Tanushri Shah 23 May 2024 • 1 min read
CFD , designed with cadence
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