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AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

RF Engineering

μWaveRiders: Cadence AWR Design Environment Advanced Customization Tips & Tricks

The AWR Design Environment is highly customizable. Advanced customization options…

• 5 min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , AWR customization , Tips/Tricks , RF design , microwave office , Visual System Simulator (VSS) , customization , scripting

Digital Design

Is your Compression Technique Unified? Wanna Explore?

Scan compression is critical for addressing the rapid rise of test costs without…

• 1 min read
scan , DFT , compression , Genus , Synthesis

System, PCB, & Package Design 

BoardSurfers: An Introduction to Dimensioning in Allegro PCB Editor

With boards becoming more complex and lightweight at the same time, designing and…

• 2 min read
17.4 , Manuafacturing , BoardSurfers , Layout , 17.4-2019 , PCB design , Allegro PCB Editor , Allegro

Computational Fluid Dynamics

From EDA to SDA – The Emergence of Intelligent System Design Automation

Technology innovation is continually transforming our user experience and disrupting…

• 6 min read
CFD , EDA , Computational Fluid Dynamics , system design

Computational Fluid Dynamics

This Week in CFD

Here are a few teasers for what you'll find in this week's round-up of CFD news and…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics , Omnis

Computational Fluid Dynamics

DoE INCITE Award for Cadence CFD

We are very excited to be part of a team selected for a Dept. of Energy INCITE Award…

• 1 min read
CFD , Aerospace , Pointwise , Computational Fluid Dynamics , fluid dynamics , high-order , HPC , Mesh Generation , LES

Breakfast Bytes

PCIe 6.0 Standard Ratified...and Cadence's Implementation

The big news about PCIe 6.0 is that the specification has been released by the PCI…

• 6 min read
pcie 6 , PCIe , pcie version 6.0

Breakfast Bytes

Tensilica Security

2021 was famous for some of the worst security issues (accompanied by obligatory…

• 4 min read
security , Tensilica , Xtensa , beyond semiconductor

Computational Fluid Dynamics

Pipistrel Reduces Energy Consumption Electric Aircraft through Propeller Optimiz…

Pipistrel used the propeller as an airborne wind turbine, by transforming the energy…

• 4 min read
CFD , Aerospace , Computational Fluid Dynamics , aviation sustainability , fluid dynamics , optimization , green aviation , Aerospace Engineering , CFD Applications , Omnis , simulation

Breakfast Bytes

Computational Fluid Dynamics, Software, and Chip Design

There are a lot of commonalities between computational fluid dynamics (CFD), software…

• 5 min read
CFD , computational software , EDA , software analysis

Life at Cadence

My Life at Cadence: Dajana Danilovic

Today’s interview features Dajana Danilovic, an application engineer based near Munich…

• 1 min read
Insights on Culture , cadence , GPTW , my life at cadence , LifeAtCadence , women in tech , great place to work , cadence emea

CFD（数値流体力学)

FINE /MARINE 10.2 国内公式リリース

FINE/Marine の最新バージョンでは、耐航性計算の高速化、抵抗計算の粗メッシュ初期化、Rhinoプラグインによるジオメトリ準備の高速化、解適合格子の改善などが行われています…

• less than a min read
CFD , naval archicture , Marine Engineering , automation , fine/marine , Computational Fluid Dynamics , fluid dynamics , CFD Applications , simulation software , japanese blog , Omnis , simulation

Computational Fluid Dynamics

This Week in CFD

Welcome, CFDers, to a new year of CFD news, applications, software, events, and general…

• 1 min read
CFD , Flashpoint , automotive engineering , Pointwise , Computational Fluid Dynamics , fluid dynamics , Mesh Generation , Omnis

Breakfast Bytes

Offtopic: Headlines

Monday is Martin Luther King Jr. Day. Breakfast Bytes will not appear and so today…

• 3 min read
offtopic

PCB設計／ICパッケージ設計

ASCENT: ブラウザベースのダッシュボードからSystem Captureの機能にアクセスする

エレクトロニクス設計のプログラムマネージャーやチームマネージャーであれば、Allegro® System Captureなどの設計ツールを直接使って仕事をすることはまずないでしょう…

• less than a min read
17.4-2019 , Allegro System Capture , japanese blog , ASCENT , 17.4-QIR3

Breakfast Bytes

Jasper User Group Best Paper 2021

The annual Jasper User Group was held in November. I've already written several posts…

• 8 min read
Jasper User Group , JUG , formal , ARM , JasperGold

PCB設計／ICパッケージ設計

IC Packagers: IC Package Designでの既製部品に関するサポート

Allegro® Package Designer Plusの17.4-2019 HotFix 019より前のバージョンでは、デザイン上でClassがICタイプの部品はすべてDie…

• 1 min read
APD , IC Packaging & SiP design , IC Packagers , Allegro Package Designer , 17.4-2019 , japanese blog

SoC and IP

Improving Performance and Throughput While Implementing FFT Using Tensilica ConnXB20…

Real-time FFT performance in Radar, Lidar, and ADAS applications is limited by data…

• 6 min read
DSP , cadence , tie , semiconductor IP , DIT , Tensilica IP , FFT

Breakfast Bytes

The State of the RISC-V Union, part II

This is part 2 of my post on DAC and RISC-V from December. The first post is here…

• 7 min read
risc-v , risc-v summit
CDNS - Fix Layout Hompage