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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

The Return of Breakfast Bytes

If you are an avid follower of Breakfast Bytes, and of course, you should be, you…

• 2 min read
covid

SoC and IP

High-Speed 112G Design and COM Dependencies

The design impairments such as SoC packaging, package-to-board impedance mismatch…

• 5 min read
high-speed , 112g , SerDes , SerDes IP , COM Dependencies , Log-Reach

Life at Cadence

Volunteering in Today’s World

Cadence recently announced its sixth Season of Giving. Giving back is a special part…

• 3 min read
Culture , Cadence Cares , cadence , giving back , Season of Giving , LifeAtCadence , life at cadence , volunteer , cadence emea

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Tips for Accelerating Power Signoff in Chip-package…

This blog discusses PLOC grouping optimization which provides the flexibility in…

• 4 min read
Voltus IC Power Integrity Solution , Chip-package Co-analysis , PLOC GROUPING OPTIMIZATION , Sigrity XtractIM , PLOC

The India Circuit

Mentor Story: Roli Sinha - Cadence Scholarship Program

Introduced five years ago, the Cadence Scholarship Program is the flagship CSR program…

• 3 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India

Computational Fluid Dynamics

This Week in CFD

As my friend Brian says, "Something weekend this way comes." But first, it's time…

• less than a min read
CFD , webinars , Computational Fluid Dynamics , CFD Applications

Verification

Re-Timer – The Key for High-Speed Signal Transmission in USB4 Systems

The objective of USB4 protocol to achieve high speed signal transmission and thereby…

• 1 min read
Re-timer , USB4 VIP , VIP , usb4 , usb4 router

System, PCB, & Package Design 

ASCENT: 3 Reasons to Use Live BOM for Your Bill of Materials

A product is only as good as its components, which makes selecting good components…

• 3 min read
17.4 , LIVE BOM , 17.4-2019 , Allegro System Capture , Part Search , ASCENT , BOM , Schematic , Allegro

PCB、IC封装：设计与仿真分析

PCB 的 DDR4 布线指南和 PCB的架构改进

计算机领域总是在持续不断地进步，始终有发展变化和更新迭代等待着我们去体验和探索。从头开始打造一台新的 PC 是一种令人愉悦的体验，有新一代标准时更是如此。说到这里…

• 1 min read
Chinese blog , DDR4 , 布线 , PCB设计 , Layout , 中文 , Allegro

Academic Network

Introducing DATE 2022 Young People Program

The DATE conference , the biggest EDA conference in Europe will find place 14-23…

• 3 min read
opdk , DATE , Career Fait , 2Horizons , Career Forum , Young People Program , DATEBarCamp

The India Circuit

DVCON India 2021 - A Quick Summary

Another DVCon India, the ‘Mecca’ for Design and Verification Engineers, took place…

• 3 min read
DVCon India , Cadence Protium , Cadence Palladium , Cadence Xcelium ML , Cadence Xcelium

Life at Cadence

Attain Functional Safety with the Midas Safety Platform

The rapid increase in innovations such as ADAS, lidar, radar, and automation has…

• 7 min read
Safety Solution , Automotive , functional safety , midas , FMEDA , ISO 26262 , ADAS , Safety Compliance

Analog/Custom Design

Spectre Tech Tips: Spectre Voltage Domain Check

This blog introduces you to the static voltage domain check in the Spectre circuit…

• 3 min read
Spectre 21.1 , Analog Simulation , Spectre Circuit Simulator , Spectre X Simulator

Computational Fluid Dynamics

February Is the Month for CFD Webinars - Register Today

In place of This Week in CFD (gotta pay them bills) I shared today overviews of the…

• less than a min read
CFD , automotive engineering , Aerospace , webinars , Pointwise , Computational Fluid Dynamics , Omnis

Life at Cadence

Functional Safety Solutions - How Hailo Ensured ISO 26262 ASIL-B (D) Compliance for…

Safety is critically important across the automotive, industrial, and aerospace and…

• 3 min read
Automotive , functional safety , cadence , Safety , midas , iso26262 , ADAS

System, PCB, & Package Design 

ASCENT: Training Insights: Connecting System Architecture Design and Implementat…

Today we take a break from our regular posts on Allegro System Capture features and…

• 3 min read
17.4 , webinar , 17.4-2019 , Design Reuse , Training Insights , Constraints , Allegro System Capture , ASCENT , Schematic , Allegro

RF /マイクロ波設計

μWaveRiders:Cadence AWR Design Environment の高度なカスタマイズのヒントとコツ

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design…

• 1 min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , AWR customization , Tips/Tricks , RF design , microwave office , japanese blog , customization , scripting , Visual System Simulator(VSS)

RF Engineering

μWaveRiders: Cadence AWR Design Environment Advanced Customization Tips & Tricks

The AWR Design Environment is highly customizable. Advanced customization options…

• 5 min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , AWR customization , Tips/Tricks , RF design , microwave office , Visual System Simulator (VSS) , customization , scripting

Digital Design

Is your Compression Technique Unified? Wanna Explore?

Scan compression is critical for addressing the rapid rise of test costs without…

• 1 min read
scan , DFT , compression , Genus , Synthesis
CDNS - Fix Layout Hompage