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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

PCB、IC封装：设计与仿真分析

如何通过团队协作解决PI问题，减少设计迭代

要按时设计一个优化的电源和一个没有板级 SI/PI 问题的 PCB 设计需要设计师、layout 工程师和 PI 工程师通过一个集成设计平台紧密合作。 面向团队的设计流程允许设计和…

• 1 min read
Chinese blog , 电源完整性 , Sigrity Aurora , DC分析 , PCB设计 , 中文 , PowerTree , 压降 , 设计同步分析 , 设计同步 , Sigrity , Allegro PCB Editor , IR drop , PowerDC , Allegro

Breakfast Bytes

EDA on AWS Graviton

At the Arm DevSummit, there were several presentations on the first day about EDA…

• 7 min read
liberate trio , cloud , graviton , aws , graviton 2 , cadence cloud , Liberate , xcelium , ARM

カスタムIC／ミックスシグナル

Virtuosity: Cdsenv Editor – Virtuoso のカスタマイズの簡素化

カスタマイズはとても重要です。アイスクリームの選択からプレミアムカーの装備まで、我々は必要または希望に応じたプロダクトのカスタマイズを求めています。 Virtuoso…

• less than a min read
Cdsenv Editor , Virtuoso Environment Variables , ICADVM18.1 , cdsenv , cdsenv variables , Virtuosity , Virtuoso Design Environment , japanese blog , Custom IC Design , IC6.1.8

Verification

Renesas Sees Success With the Full System Solution

If you’re looking for an example of how well the Cadence flow fits together, look…

• 2 min read
iwb , Perspec , Palladium , Renesas , system performance analyzer , system testbench generator

System, PCB, & Package Design 

BoardSurfers: Translating Allegro Database to Readable Format Using 'Extracta'

In the process of developing a PCB design, a multitude of experts are involved in…

• 5 min read
APD+ , 17.4 , extracta , Allegro PCB Editor

Analog/Custom Design

Virtuoso Video Diary: Walkthrough of Top 5 Latest Features of Voltus-Fi-XL

Are you curious to know about the recent developments in Voltus-Fi Custom Power Integrity…

• 4 min read
ICADVM18.1 , Voltus-Fi-XL , PGV , Annotation Browser , ICADVM20.1 , IC6.1.8 , EMIR

Life at Cadence

Échale Ganas (Give It Your All): A Reflection on Hispanic Heritage Month

For Hispanic Americans and Latino Americans, the American dream is more than just…

• 3 min read
Insights on Culture , inclusion , Latina , latinx , HispanicHeritageMonth , Hispanic , Latino

Breakfast Bytes

Pegasus Certified Down to 3nm at TSMC

EDA tools have a primary challenge: to be good at whatever it is they do. They have…

• 4 min read
Physical verification , n5 , certified , pegasus , DRC , TSMC , 16FFC , n7

The India Circuit

Mousumi Ghorai: A Story of Courage and Confidence

Following on from my last blog about the Cadence Scholarship Program, here is the…

• 3 min read
CadenceCares , CadenceScholarshipProgram , cadence , WomenEmpowerment , GirlPower

Breakfast Bytes

Electromagnetic Compliance: Anechoic Chamber Not Required

Yesterday, I reported on Paul Cunningham's announcement of a new product, System…

• 4 min read
Clarity 3D Transient Solver , electronmagnetic susceptibility , electromagnetic compliance , cloudburst , cadence cloud , clarity

Life at Cadence

10 Things that Make a Terrific Manager

It is often said that employees join companies but leave managers. If you think back…

• 5 min read
leadership

Analog/Custom Design

Virtuoso Meets Maxwell: Quick Start for Virtuoso RF Solution

The shift to heterogeneous integration of module designs implies a transition from…

• 4 min read
Rapid Adoption Kit , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Layout EXL , Virtuoso MultiTech , ICADVM20.1 , Cadence SiP Layout , Custom IC Design , RAKs , Allegro , VMM

System, PCB, & Package Design 

IC Packagers: Accurate Masking of Your Substrate Layers

Soldermask and its brethren are stable in the EDA design industry. These layers control…

• 5 min read
IC Packaging & SiP design , Allegro Package Designer , 17.4-2019

Breakfast Bytes

System VIP: Logistics for Cache-Coherent Multiprocessor Systems

Today, at CadenceLIVE Europe, Paul Cunningham, the GM of the verification business…

• 5 min read
system vip , risc-v , system d&v , x86 , Protium , VIP , Palladium , xcelium , ARM

定制IC芯片设计

Virtuoso Meets Maxwell: 裸片版图导出（Die Export）功能改头换面

大家好! 今天，我想给大家介绍Virtuoso RF解决方案中裸片版图导出（Die Export）的最新改进功能，其中大多数功能都已在ICADVM18.1 ISR10中发布…

• 4 min read
Chinese blog , ICADVM18.1 , Virtuoso Meets Maxwell , Advanced Node , Virtuoso RF Solution , Virtuoso RF , Layout EXL , Wirebond , virtuoso system design platform , shape-based die , RF design , SKILL

Analog/Custom Design

Virtuosity: Verification in Virtuoso ADE Verifier - The Reliability Way!

Starting from the IC6.1.8/ICADVM18.1 ISR12 releases, Virtuoso ADE Verifier supports…

• 7 min read
verifier , Cadence blogs , ICADVM18.1 , custom/analog , Analog Simulation , verification plan , analog , ADE , Mixed-Signal , reliability options , Virtuoso Analog Design Environment , Monte Carlo , Virtuoso , Analog Design Environment , Virtuosity , implementations , mixed signal , Verifier Run Plan , reliability analysis , Custom IC Design , requirements , Custom IC , ADE Verifier , IC6.1.8 , reliability , Assembler , Verifier new feature , ADE Assembler , verification

Breakfast Bytes

Arm and NVIDIA: Simon Segars and Jensen Huang

What used to be face-to-face Arm TechCon has turned into a virtual conference under…

• 8 min read
Simon Segars , NVIDIA , ARM , jensen huang

Breakfast Bytes

Sunday Brunch Video for 11th October 2020

https://youtu.be/0oRah8lCf4M Made in front of my TV Monday: Jasper User Group 2020…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

全方位了解DDR 布线

本文要点： DDR 内存布线的重要性及布线时的关键注意事项。 从扇出布线 (escape routing) 和端接，到布线和高密度互连 (HDI) 设计的布线技巧…

• 1 min read
Chinese blog , ddr5 , 布线 , PCB设计 , 中文 , 高密度互连 , DDR , 扇出布线 , 内存设计
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