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Featured

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
Corporate 31 Jul 2026 • 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
Corporate 27 Jul 2026 • 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
Corporate 26 Jul 2026 • 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
Corporate 22 Jul 2026 • 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent
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Blog - Post List
Latest blogs

Verification

JasperGold FPV: Asynchronous Designs? No Problem!

Asynchronous designs happen. They’re not particularly easy to verify, but sometimes…

XTeam 16 Sep 2020 • 1 min read
Functional Verification , jaspergold fpv , asynchronous , JasperGold

Verification

Cadence Is Arm-and-Arm with Arm: Fast Models for Fast Prototyping

If you’re not familiar with the Arm/Cadence collaboration , you’ve been missing out…

XTeam 16 Sep 2020 • 1 min read
Fast Models , Protium , Palladium , ARM

Breakfast Bytes

RISC-V State of the Universe

A couple of weeks ago was the RISC-V Global Forum. This was truly global, in that…

Paul McLellan 16 Sep 2020 • 5 min read
risc-v , isa , patterson , asanovic

Digital Design

Join Us for a Deep-Dive into Block Implementation with Innovus Using the Stylus Common…

If you are looking for a comprehensive training on block implementation with Innovus…

Attila Zsigmond 15 Sep 2020 • 2 min read
digital badge , blended training , training bytes , Digital Implementation , Innovus , online training , Floorplanning and Prototyping , Cadence support

System, PCB, & Package Design 

BoardSurfers: Installation Know-How: Which Installation Method is Right for You?

Installing new software seems like a daunting task for most of us. You may feel burdened…

Shikha Jain 15 Sep 2020 • 4 min read
17.4 , Allegro OrCAD Installer , 17.4-2019 , Download Manager , OrCAD , Allegro

System, PCB, & Package Design 

IC Packagers: Shrinking Dies Inside the Package Layout

There are many reasons a die’s size in the package doesn’t match the design size…

Tyler 15 Sep 2020 • 6 min read
IC Packaging , Allegro Package Designer , 17.4-2019

Breakfast Bytes

PSpice for TI

Texas Instruments (TI) is the biggest analog semiconductor company in the world.…

Paul McLellan 15 Sep 2020 • 3 min read
pspice-ti , analog , PSPICE , OrCAD , Texas Instruments , TI

カスタムIC/ミックスシグナル

Start Your Engines: ブログメーターの確認

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

Custom IC Japan 14 Sep 2020 • less than a min read
CLIPS , mixed signal design , Functional Verification , AMS Designer , Unified Netlister , AMSD Flex Mode , japanese blog , mixed-signal verification

Breakfast Bytes

What to Do About IP Developed Before ISO 26262?

If you have paid even passing attention to what has been going on in automotive functional…

Paul McLellan 14 Sep 2020 • 4 min read
asil ready , Automotive , functional safety , ASIL , ISO 26262 , fusa

Breakfast Bytes

Sunday Brunch Video for 13th September 2020

https://youtu.be/aqlmfd3g5G0 Made in "Jaipur, India" Monday: Labor Day Tuesday…

Paul McLellan 13 Sep 2020 • less than a min read
sunday brunch

Verification

Celsius on Protium - Using Cadence Tools to Improve Cadence Tools?

The Cadence tool flow is the most comprehensive flow around. If there is an EDA need…

XTeam 11 Sep 2020 • 1 min read
celsius , Functional Verification , Protium

Digital Design

Library Characterization Tidbits: The Perfect Solution for Validating Libraries

A library view contains electrical information that is used throughout design implementation…

HelenShi 11 Sep 2020 • 2 min read
Liberate LV , library characterization , Library Characterization Tidbit , Digital Implementation , Liberate Characterization Portfolio , library validation

Breakfast Bytes

Use Your Imagination to Get Smaller, Faster Chips

At the recent CadenceLIVE Americas, Nick Loebner of Imagination Technologies presented…

Paul McLellan 11 Sep 2020 • 3 min read
Genus , GPU , Imagination Technologies , Imagination , Innovus , digital full flow , ispatial

カスタムIC/ミックスシグナル

Virtuoso Video Diary: 信頼性解析の改善

IC6.1.8/ICADVM18.1 ISR3のVirtuoso® ADE Assembler および Virtuoso ADE Explorer で、信頼性解析の実行方法を完全に変更する…

Custom IC Japan 10 Sep 2020 • less than a min read
Stress Analysis , Cadence blogs , ICADVM18.1 , ADE Explorer , Virtuoso Analog Design Environment , Virtuoso Video Diary , aging , japanese blog , reliability analysis , Custom IC Design , IC6.1.8 , ADE Assembler

Analog/Custom Design

Virtuosity: Examining Post-Layout Capacitance Using Virtuoso ADE Assembler and ADE…

Post-Layout has become a hot topic recently. This has kept me and several other engineers…

Arja H 10 Sep 2020 • 2 min read
Analog Design Environment , PAD , ICADVM18.1 , ADE Explorer , Spectre , Virtuosity , Custom IC Design , IC6.1.8 , parasitics

Breakfast Bytes

HOT CHIPS: The Space Race for the Biggest ML Machine

At the recent HOT CHIPS, the Sunday morning tutorial was on scale out of deep learning…

Paul McLellan 10 Sep 2020 • 5 min read
GPU , deep learning , tpu , NVIDIA , cerebras , wafer scale integration , google , training , mlperf

Verification

Mellanox's Tips and Tricks for Maximizing Your Palladium Unit

Looking to learn more about the best practices for emulating today’s billion-gate…

XTeam 9 Sep 2020 • 1 min read
Functional Verification , mellanox , Palladium , Tips

Breakfast Bytes

OIP Ecosystem Forum 2020

Last Tuesday was the virtual TSMC OIP Ecosystem Forum. Apart from being virtual,…

Paul McLellan 9 Sep 2020 • 3 min read
OIP , Automotive , n5 , oip ecosystem summit , ultra low power , n3 , TSMC , 16FFC , n7 , n6 , n12e , 3dfabric

System, PCB, & Package Design 

BoardSurfers: Find by Name or Find by Query - That is the Question!

You must be using find utility day in and day out, but if you are unfamiliar with…

BarbS 8 Sep 2020 • 9 min read
Find command , APD , PCB Editor , FIND , Find result , Find by Query
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