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Breakfast Bytes

Celsius and Voltus: 2+2=5

I recently attended a webinar presented by Rajat Chaudhry, who is a Product Engineering…

Paul McLellan 17 Jul 2020 • 6 min read

celsius , Voltus , thermal

Analog/Custom Design

Virtuosity: In the Line of Veri-Fire - Episode 2

Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso…

Team ADE Verifier 16 Jul 2020 • 6 min read

verifier , Analog Design Environment , Cadence blogs , ICADVM18.1 , Analog Coverage , verification plan , analog , ADE , analog verification , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , ADE Blog Series , FAQ , implementations , analog design , Custom IC Design , requirements , Custom IC , ADE Verifier , IC6.1.8 , Assembler , Verifier new feature , custom design technology , ADE Assembler , verification

Breakfast Bytes

Clarity, Sigrity, EMX, and AWR: So Many EM Solvers to Choose From…

Cadence has multiple electromagnetic (EM) technologies within its product portfolio…

Paul McLellan 16 Jul 2020 • 6 min read

RF , AXIEM , Virtuoso RF , EMX , Sigrity , EM , clarity

Academic Network

Great Collaboration on Teaching Verification with Bosch Sensortec and HTW Dresde…

The HTW Dresden - University of Applied Sciences offers several courses in the area…

Anton Klotz 15 Jul 2020 • 3 min read

HTW Dresden , Specman , Cadence Academic Network , Bosch Sensortec , verification

Breakfast Bytes

Analyzing On-Chip RF Passives

RF stands for radio-frequency. Obviously, this covers radios of all types, but as…

Paul McLellan 15 Jul 2020 • 7 min read

RF , EMX , RF design , radio

Digital Design

iSpatial Flow in Genus: A Modern Approach for Physical Synthesis

With advanced-process nodes, the physical delay of a standard cell, net delay, and…

Neha Joshi 14 Jul 2020 • less than a min read

Genus , video , Logic Design , physical implementation

System, PCB, & Package Design

BoardSurfers: Training Insights: Adding and Re-Ordering Mask Layers

One idea that completely revolutionized the concept of PCB making is adding layers…

Shreyansh 14 Jul 2020 • 3 min read

17.4 , 17.4-2019 , PCB design , Allegro PCB Editor

System, PCB, & Package Design

IC Packagers: Renaming Nets in a Layout

As the component count increases in package/interposer designs, many more of you…

Tyler 14 Jul 2020 • 4 min read

17.4 , IC Packaging , Allegro Package Designer , 17.4-2019

Breakfast Bytes

Zhuo Li, DAC Chair, Plus Cadence@DAC

Yesterday was my DAC Preview post. As it happens, Cadence's Zhuo Li is this year…

Paul McLellan 14 Jul 2020 • 4 min read

57dac , DAC , Accellera , Design Automation Conference

カスタムIC／ミックスシグナル

Virtuosity: 洗練されたExtractedビュー

Cadence® Quantus Smart Viewは、Virtuoso環境の次世代のExtracted Viewです。Smart Viewは、Extracted…

Custom IC Japan 13 Jul 2020 • 1 min read

Smart View , PAD , ICADVM18.1 , ADE Explorer , Virtuoso , Parastics , Virtuosity , japanese blog , Quantus , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

System, PCB, & Package Design

Streamline Your PCB Design Flow with In-Design and Post-Route Power Integrity An…

Designing an optimized power supply and a PCB without board-level SI/PI problems…

Sigrity 13 Jul 2020 • 8 min read

PCB , Allegro PCB Design Editor , Power Integrity Analysis , Sigrity Aurora , in-design , PowerTree , DC analysis , IR drop , PowerDC

Breakfast Bytes

DAC Preview 2020

It is the 57th Design Automation Conference later this month from July 20 to 24.…

Paul McLellan 13 Jul 2020 • 6 min read

57dac , DAC , Design Automation Conference

Breakfast Bytes

Sunday Brunch Video for 12th July 2020

https://youtu.be/kA0y55I9zMA Made on my balcony (camera Carey Guo) Monday: Cadence…

Paul McLellan 12 Jul 2020 • less than a min read

sunday brunch

カスタムIC／ミックスシグナル

Virtuosity: 新しいアイダイアグラムの測定

Virtuoso® Visualization and Analysis のEye Diagram アシスタントを使用すると、アイダイアグラムを作成したり、マスクを追加したり…

Custom IC Japan 10 Jul 2020 • less than a min read

Eye Mask , Analog Design Environment , ViVa-XL , ADE Explorer , Explorer , ADE XL , ADE , eye diagram , ViVA , Virtuosity , japanese blog , Custom IC Design , ADE Assembler