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PCB、IC封装：设计与仿真分析

Ken的博客系列之六 | 千兆位串行链路接口的SI方法

作者：Ken Willis 上一篇：高效的互连提取使用IBIS-AMI模型进行仿真此时，SerDes元器件供应商应该已经提供了所需的IBIS-AMI模型…

Sigrity 13 Sep 2019 • less than a min read

PCB , SI , Chinese blog , ddr5 , 仿真分析 , DDR4 , equalization , IBIS-AMI , 中文 , SerDes , Sigrity , SystemSI , 信号完整性

Breakfast Bytes

Intelligent System Design

Yesterday in my post Intelligent Systems , I wrote about how the imperative for differentiated…

Paul McLellan 13 Sep 2019 • 5 min read

system analysis , pervasive intelligence , design excellence , intelligent system design , system innovation

Breakfast Bytes

Intelligent Systems

Cadence's goal is to empower engineers at semiconductor and systems companies to…

Paul McLellan 12 Sep 2019 • 4 min read

intelligent system design

Digital Design

Safety and Aging in IoT Devices: What We Know Today

How do we achieve highly accurate aging data models for critical circuits in automotive…

XTeam 11 Sep 2019 • 1 min read

iot devices , DAC 2019 , aging , GlobalFoundries

定制IC芯片设计

Virtuosity: Spring-Cleaned Virtuoso Doc Closet

如需了解IC6.1.8 和ICADVM18.1相关的最新文档，请继续阅读.

Rishu Misri Jaggi 11 Sep 2019 • less than a min read

legato , Chinese blog , Virtuoso Schematic Editor , ICADVM18.1 , Routing , ADE L , Virtuoso RF , Layout EXL , layout XL , Layout L , Cadence Help , Virtuoso Doc , Virtuoso Design Environment , New in EDA , Virtuoso Layout Suite EXL , IC6.1.8

Breakfast Bytes

EDPS Preview 2019

EDPS, the Electronic Design Process Symposium, is coming up next Monday. It will…

Paul McLellan 11 Sep 2019 • 3 min read

deep learning , 3DIC , EDPS , more than Moore , AI

Life at Cadence

How to Land a Job at Cadence: Recruiters Share Their Best Tips for Standing Out and…

As we send off the last of our 2019 Summer Interns ( read more about their experience…

Ashley Sneathen 10 Sep 2019 • 4 min read

intern , Student , internship

System, PCB, & Package Design

IC Packagers: How Far Away are You?

Layout design is all about clearances. Daily challenges come from maintaining consistent…

Tyler 10 Sep 2019 • 3 min read

SiP Layout

System, PCB, & Package Design

BoardSurfers: PCB Electronics - Electrical Constraints

Whether it's NASA's space missions or a school camping trip; building a cutting-edge…

mrigashira 10 Sep 2019 • 3 min read

Constraint Manager , Allegro Package Designer , Allegro PCB Editor , SiP Layout

Analog/Custom Design

Virtuoso IC6.1.8 ISR6 and ICADVM18.1 ISR6 Now Available

The IC6.1.8 ISR6 and ICADVM18.1 ISR6 production releases are now available for download…

Virtuoso Release Team 10 Sep 2019 • 2 min read

Analog Design Environment , Cadence blogs , ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , Automated Device-Level Placement and Routing , Automatic Placement , Interactive and Assisted Routing , IC Release Announcement blog , Virtuoso RF , Layout EXL , ADE , Mixed-Signal , Layout , Virtuoso , advanced nodes , New in EDA , Virtuoso EM Solver , Custom IC Design , Virtuoso Layout Suite , Custom IC , ADE Verifier , IC6.1.8 , ADE Assembler

Breakfast Bytes

CDNLive India 2019: NXP and More

Last week I covered Day 1 of CDNLive India . Today it is the turn of verification…

Paul McLellan 10 Sep 2019 • 6 min read

NXP , CDNLive India , CDNLive

Analog/Custom Design

Virtuoso Meets Maxwell: Add Some MAGic to Your ElectroMAGnetic Analysis

If you’ve ever seen a great magician at work, you know that their talent lies in…

kfullerton 9 Sep 2019 • 4 min read

ICADVM18.1 , Virtuoso New Design Platform , video , Virtuoso Meets Maxwell , Virtuoso RF , Electromagnetic analysis , EM Analyis , RF design , Custom IC Design , Virtuoso Layout Suite

Breakfast Bytes

HOT CHIPS: In-DRAM Compute

Something that has been discussed for years is the fact that we could add processors…

Paul McLellan 9 Sep 2019 • 4 min read

pim , hot chips , processor in memory

Verification

Dimensions to Verifying a USB4 Design

Verification of a USB4 router design is not just about USB4 but also about the inclusion…

Neelabh 8 Sep 2019 • 2 min read

Verification IP , Router , DisplayPort , USB , usb4 , PCIe , USB3 , tunneling

Breakfast Bytes

Sunday Brunch Video for 8th September 2019

https://youtu.be/AvimlRMDZng Made at Cadence parking lot (camera Steve Brown) Monday…

Paul McLellan 8 Sep 2019 • less than a min read

sunday brunch

PCB、IC封装：设计与仿真分析

Ken的博客系列之五 | 千兆位串行链路接口的SI方法

作者：Ken Willis 上一篇：启用约束驱动设计高效的互连提取一旦物理layout完成（或者至少串行链路差分对的布线完成），就可以进行布局后验证。需要决定使用多大的带宽进行模型提取…

Sigrity 6 Sep 2019 • less than a min read

SI , Chinese blog , ddr5 , 仿真分析 , DDR4 , IBIS-AMI , 中文 , SerDes , Sigrity , SystemSI , 信号完整性 , SI分析与建模

Breakfast Bytes

Pervasive Intelligence

The biggest change in technology over the last five or ten years is the sudden kicking…

Paul McLellan 6 Sep 2019 • 2 min read

pervasive intelligence , design excellence , intelligent system design

Breakfast Bytes

CDNLive India 2019: Mediatek and More

If you live in California, as I do, then India is a long way away. It is 11½ hours…

Paul McLellan 6 Sep 2019 • 5 min read

CDNLive India , CDNLive , mediatek

Analog/Custom Design

Virtuosity: Support for Stacked Devices in Modgen

This blog provides an overview of the support for stacked devices in Modgen. This…

Aneesh Shastry 6 Sep 2019 • 3 min read

Modgen On Canvas , MODGEN , Module Generator , stacked devices , modgen stacks , Virtuoso , Virtuosity , Custom IC Design , modgens , Virtuoso Layout Suite , Virtuoso Layout Suite GXL

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