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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

IC Packagers: Don’t Get Stranded on Islands, Delete Them!

No, this isn’t a Hollywood movie. We’re talking about pieces of plane shapes with…

• 4 min read
Allegro Package Designer , Allegro PCB Editor

Digital Design

Are You Stuck While Synthesizing Your Design Due to Low-Power Issues? We Have the…

Optimizing power can be a very convoluted and crucial process. To make design chips…

• 1 min read
Low Power , Logic Design

Breakfast Bytes

Linley Spring Processor Conference—In Your Own Living Room

The annual Linley Spring Processor Conference is coming up next week. It was planned…

• 4 min read
deep learning , linley processor conference , linley group , neural networks , AI

Breakfast Bytes

RSA: Emerging Threats, Ransomware, and IoT

I attended the recent RSA Conference in San Francisco. I wrote a post about some…

• 4 min read
security , ransomware , rsa conference , rsa , IoT

System, PCB, & Package Design 

BoardSurfers: Footprints for Silicon - Two Steps to Creating PCB Footprints

Longfellow's metaphorical footprints on the sands of time is more profound and eternal…

• 3 min read
Allegro PCB Editor

Breakfast Bytes

The Mythical Man-Month

This is a continuation of yesterday's post Fred Brooks "It Is a Humbling Experience…

• 5 min read
fred brooks , mythical man-month

Analog/Custom Design

Virtuosity: Are Your Layout Design Mansions Correct-by-Construction?

Do you want to create designs that are correct by construction? Read along this blog…

• 3 min read
ICADVM18.1 , Advanced Node , Layout Suite , width spacing patterns , Layout , Virtuoso , Virtuosity , usability , Custom IC Design , ux

Breakfast Bytes

Fred Brooks: "It Is a Humbling Experience to Make a Multi-Million Dollar Mistake…

Cadence's Intelligent System Design strategy is about designing the systems of today…

• 4 min read
fred brooks , frederick brooks , mythical man month , os/360

Breakfast Bytes

RSA 2020: The Cryptographers' Panel

One of the big draws on the first day of the RSA Conference is always "The Cryptographers…

• 8 min read
security , rsa conference , rsa , cryptographers' panel

Analog/Custom Design

Virtuoso IC6.1.8 ISR10 and ICADVM18.1 ISR10 Now Available

The IC6.1.8 ISR10 and ICADVM18.1 ISR10 production releases are now available for…

• 3 min read
Cadence blogs , ICADVM18.1 , ADE Explorer , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Virtuoso RF , Virtuoso Analog Design Environment , Virtuoso , IC Release Blog , Virtuoso Layout Suite EXL , Virtuoso Layout Suite , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

Academic Network

How to Get Remote Access to Cadence Academic Tools and Licenses

With the ever-evolving workplace and classroom, we know that the way we work and…

• 4 min read
Europractice , Cadence Academic Network , remote access , EDA , CMC Microsystems , university program

System, PCB, & Package Design 

IC Packagers: Identify Your Components

We’ve all seen bar codes and the more modern QR codes. They’re everywhere you go…

• 2 min read
Allegro Package Designer , Allegro PCB Editor

Breakfast Bytes

2020 Is the Year of DDR5

I talked recently to Marc Greenberg, one of Cadence's experts on the memory market…

• 3 min read
ddr5 , Memory , DDR4

Digital Design

Library Characterization Tidbits: Validating Libraries Effectively

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for…

• 3 min read
Liberate LV , timing validation , Digital Implementation , interpolation error , library validation , RAKs

Analog/Custom Design

Virtuoso Meets Maxwell: Help with Electromagnetic Analysis - Part V

Here is another blog in the multi-part series that aims at providing in-depth details…

• 9 min read
EM Analysis , ICADVM18.1 , VRF , Virtuoso Layout EXL , ports , Virtuoso RF , Electromagnetic analysis , Virtuoso , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

Turing Award: Ed Catmull and Pat Hanrahan

Last week, the ACM announced this year's Turing Award would go to Pat Hanrahan and…

• 5 min read
vlsi technology , turing award , graphics

Breakfast Bytes

Sunday Brunch Video for 22nd March 2020

https://youtu.be/b7ixzahr85s Made on my balcony (camera Carey Guo) Monday: Another…

• less than a min read
sunday brunch

Breakfast Bytes

Netflix and C...adence

Earlier in the week, I wrote about a couple of videos from Intel, about semiconductor…

• 1 min read
sunday brunch , video , intelligent system design

Breakfast Bytes

RSA 2020: From Sulu to Penn & Teller

I attended the RSA Conference in San Francisco recently. I guess that is going to…

• 6 min read
security , rsa conference , rsa
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