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Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent
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Blog - Post List
Latest blogs

Breakfast Bytes

Xcelium ML: Black-Belt Verification Engineer in a Tool

What if I told you I knew someone who could improve your regression efficiency: make…

• 4 min read
deep learning , xcelium ml , machine learning , DVcon , xcelium , simulation

Analog/Custom Design

Virtuoso Meets Maxwell: Magic! – Dynamic Voiding in Virtuoso RF Solution

While SiP Layout Option is – and continues to be – one of the most complete solutions…

• 7 min read
ICADVM18.1 , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Dynamic Shapes , Dynamic Voiding , Custom IC Design

System, PCB, & Package Design 

BoardSurfers: Allegro In-Design Crosstalk Analysis: Signal Integrity Simulations…

Crosstalk is the transfer of unwanted signals from an “aggressor” net to a “victim…

• 2 min read
PCB design and layout , PCB Signal integrity , Allegro PCB Editor , Allegro

System, PCB, & Package Design 

IC Packagers: Make Acute Angles a Sharp Problem of the Past

Sharp angles, whether they create a spike in a poured shape or form an acid trap…

• 5 min read
Allegro Package Designer , 17.4-2019

Breakfast Bytes

Cadence Executives on Computational Software

CadenceLIVE starts today, Tuesday, August 11, and runs through Thursday. One thing…

• 3 min read
computational software , cadencelive

カスタムIC／ミックスシグナル

Virtuosity: Multi-Technology Simulation (MTS)の実行方法は？

マルチ・テクノロジ・シミュレーション(Multi-Technology Simulation; MTS)を Virtuoso® ADE Explorer と Virtuoso…

• less than a min read
Explorer , Rapid Adoption Kit , Virtuoso , Spectre , ADE-XL , Virtuosity , japanese blog , Custom IC Design , Assembler , ADE Assembler

Digital Design

Voltus Voice: Demystifying ESD – Touch Ground with a Designer-Centric Protection…

This blog highlights the key capabilities and benefits of the Voltus ESD analysis…

• 5 min read
effective resistance , Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , Power Signoff , electrostatic discharge , current density , Power Integrity , Innovus , Charged Device Model , Full-Chip , ESD

Breakfast Bytes

120th Anniversary of Hilbert's Problems

The computational software algorithms used in EDA are fundamentally mathematical…

• 3 min read
hilbert's problems , computational software , millennium prize problems

PCB、IC封装：设计与仿真分析

电子系统设计中进行片上热分析的四大挑战与应对

在大约 138 亿年前的创生之初，我们的宇宙在 0 到 10-43 (10^(-43))秒的短短时间里产生和释放了大量的热量或能量，这在理论上得到了各种模型和测量数据的支持…

• less than a min read
Celsius Thermal Solver , 热 , PI , Chinese blog , 电源完整性 , 热分析 , 3D 分析 , EE Thermal , 电热协同仿真 , 热传输 , Voltus , 中文 , 系统分析 , IC封装 , 异质封装

Breakfast Bytes

Weekend Update 2

This is my second update post where I cover things that I have covered before, and…

• 2 min read

Breakfast Bytes

Rigid-Flex

Rigid-flex sounds like something that might be a Crossfit workout-of-the-day. But…

• 5 min read
PCB , Rigid-Flex , Allegro

Breakfast Bytes

Why Attend CadenceLIVE Americas?

We renamed our user conference to CadenceLIVE (from CDNLive) just in time for it…

• 5 min read
CDNLive , cadencelive 2020 , cadencelive americas , cadencelive

PCB設計／ICパッケージ設計

BoardSurfers：17.4-2019 HotFix 007 for Electrical CAD-Mechanical CAD Library Creator…

Library Creator 17.4-2019 HotFix 007のアップデートより、Templatesダイアログ全体に改良が加えられ、テンプレートを見つけて選択しやすくなりました…

• less than a min read
Library Creator , PCB , 17.4 , PCB Editor , ECAD-MCAD Library Creator , japanese blog

PCB設計／ICパッケージ設計

2020年5月リリース、OrCAD / Allegro 17.4-2019 HotFix 007 の新機能ハイライト

OrCAD® 及び Allegro® のHotFix 007 (QIR 1)が Cadence Downloads からダウンロードできます。この新リリースでは…

• less than a min read
PCB , 17.4 , OrCAD Capture , APD , PCB Editor , japanese blog

System, PCB, & Package Design 

BoardSurfers: Installation Know-How: Six Things You Need to Know Before Installing…

Installation of software applications depends upon certain factors such as system…

• 4 min read
Allegro OrCAD Installer , OrCAD , Allegro

System, PCB, & Package Design 

IC Packagers: Removing and Replacing an Area of a Design

If you ever have the need to remove an area of your design, you may find it to be…

• 4 min read
IC Package , Allegro X Advanced Package Designer , 17.4-2019

Breakfast Bytes

Accellera Functional Safety

This is my last post about DAC 2020. During DAC Accellera had a workshop about functional…

• 8 min read
Automotive , functional safety , Accellera , fusa

Academic Network

Custom IC, Analog, and RF Design Training Deep Dive: Part 2

Let’s continue exploring the training courses related to Custom IC, Analog, and RF…

• 5 min read
Europractice , Cadence Academic Network , CMC Microsystems , Virtuoso , online training , university program

Breakfast Bytes

DAC 2020: Chips in 2030

In 2015, soon after I rejoined Cadence, I went to IEDM, the International Electron…

• 6 min read
57dac , DAC , Design Automation Conference
CDNS - Fix Layout Hompage