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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Breakfast Bytes

TSMC: Mobile, HPC, IoT, Automotive...and Packaging

This is the third post about the TSMC Technology Symposium that was held on May 1st…

• 11 min read
Automotive , IoT , TSMC , TSMC Technology Symposium , mobile

Breakfast Bytes

What's For Breakfast? Video Preview May 21st to 25th 2018

https://youtu.be/AmlYRYzIHtY Coming from my office (camera Sean, guest star Alexa…

• less than a min read
accelerating AI , CDNLive , embedded vision , Tensilica , gdpr , MEMS

The India Circuit

Inspiration, Networking and Food For Thought

Recently I had the opportunity to attend the Society of Women Engineers (SWE) Conference…

• 4 min read
society of women engineers , SWE , women leaders

Breakfast Bytes

CDNLive: Testing Times in Munich

Test is the red headed step child of EDA. FinFETs, self-aligned quadruple patterning…

• 9 min read
modus test , CDNLive , Scan test , modus , imec , Test

Academic Network

Status of Verification Education in Academia

Since I’ve started working for Cadence Academic Network three years ago, when talking…

• 3 min read
survey , Cadence Academic Network , Functional Verification , young professionals , Incisive simulator

Breakfast Bytes

Agile Development of Custom Hardware

It was back in 2016 that I first heard about RISC-V, and the Raven implementation…

• 5 min read
bag , chisel , agile software development , waterfall , raven , agile hardware development , UC Berkeley , Agile

Breakfast Bytes

Compromising a Fortune 500 Company...Without Hacking a Thing

Rachel Tobac and Joe Gray opened their talk at RSA by highlighting how important…

• 6 min read
security , rsa conference , rsa , social engineering

System, PCB, & Package Design 

Power-Aware SI DDR4 Simulation: You Have a Choice!

Simultaneous switching noise (SSN) caused by simultaneous switching outputs (SSO…

• 4 min read
Speed2000 , DDR4 , FDTD , power-aware , SystemSI , SSN

Breakfast Bytes

CDNLive EMEA, Driving to the Future

This week it has been the 13th European CDNLive, held in Unertschleißheim in the…

• 7 min read
Automotive , legato , CDNLive , CDNLive EMEA , AI

System, PCB, & Package Design 

Make Reliable Designs That Won’t Fail In The Real World!

Heard about the ongoing recalls in the Automotive and Cellphone industry? Let's address…

• less than a min read
RF , OrCAD Capture , PSPICE , PCB design , simulation

Breakfast Bytes

Digital Marketing in EDA...with No Hands on the Wheel

Years (decades) ago, Robert Townsend, the CEO of Avis, faced a problem. Hertz was…

• 5 min read
google , YouTube , digital marketing , Twitter , adwords , onespin , esd alliance

Whiteboard Wednesdays

Whiteboard Wednesday - Introducing the DFI 5.0 Interface Standard

In this week’s Whiteboard Wednesday, John MacLaren, chairman of the DDR PHY Interface…

• less than a min read
DDR Controller , Whiteboard Wednesdays , DDR PHY

Breakfast Bytes

Legato: Smooth Reliability for Automobiles

In his keynote at ICCAD in 2014, Bosch's VP engineering Peter van Staa said that…

• 4 min read
legato , CDNLive , CDNLive EMEA , reliability

Breakfast Bytes

What's For Breakfast? Video Preview May 14th to 18th 2018

https://youtu.be/T4Pu_l6upso Coming from Englischergarten Munich (camera Andy…

• less than a min read
bag , CDNLive , efpga , chisel , CDNLive EMEA , TSMC , TSMC Technology Symposium , FPGA

Breakfast Bytes

TSMC's Fab Plans, and More

The TSMC Technology Symposium took place recently. I grouped all the process and…

• 5 min read
gigafab , TSMC , TSMC Technology Symposium

Breakfast Bytes

TSMC Technology Symposium 2018

This week it was the TSMC Technology Symposium in Silicon Valley. Dave Keller, president…

• 9 min read
n5 , TSMC , TSMC Technology Symposium , n7+ , n7 , 5nm , 7nm

Verification

Leading the Charge: Cadence Announces New Verification IP for UFS 3.0, CoaxPress…

Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence…

• 1 min read
hyperRAM , Functional Verification , coaxpress , UFS , press release

Breakfast Bytes

What's For Breakfast? Video Preview May 7th to 11th 2018

https://youtu.be/OJRKUHltc1c Coming from Teske's Germania (camera Sean) Monday…

• less than a min read
CDNLive EMEA , TSMC , TSMC Technology Symposium , digital marketing , social engineering , esd alliance

Breakfast Bytes

The San Jose Tech Museum

Last summer, I did a series of posts about technology museums. If you missed them…

• 6 min read
security , san jose , the tech , body worlds
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