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Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Latest blogs

SoC and IP

Cadence at Flash Memory Summit 2016: Octal SPI, eMMC 5.1, ONFi 4, and Tensilica SSD…

If you design with flash memory components or IP solutions, head on over to the Santa…

• 1 min read
Verification IP , Design IP , Memory , VIP , Tensilica , semiconductor IP , Design and Verification IP , Design IP and Verification IP , memories

Breakfast Bytes

Smartphones: Linley's Annual Review

Last week was the Linley Mobile Conference, although it is now the Mobile and Wearables…

• 3 min read
Apple , Samsung , wearables , mobile , Smartphone , Huawei

Analog/Custom Design

Virtuoso Variation Option: Reliable High-Yield Design with Scaled-Sigma Sampling

What’s Scaled-Sigma Sampling? Scaled-sigma sampling (SSS) is an efficient algorithm…

• 4 min read
Variability Aware Design , scaled sigma sampling , ADE , IEEE , Variation , yield

Analog/Custom Design

Analog Design Resonance: Quick and Efficient Regression Scripts–Now Possible with…

The new Virtuoso ADE product suite is packaged with a lot of easy-to-use, productivity…

• 3 min read
ADE Explorer , ADE , Custom IC Design , ADE Assembler

Breakfast Bytes

CDNLive Boston Preview

The full agenda for CDNLive Boston is now available. This is really "East Coast"…

• 2 min read
CDNLive , Power Integrity , cdnlive boston , Boston , Signal Integrity , Breakfast Bytes

Breakfast Bytes

Nokia's Rise and Fall...and Maybe Rise Again

If you live in the US, then it is hard to believe how dominant Nokia was in mobile…

• 7 min read
microsoft , nokia , elop , mobile , Breakfast Bytes , iPhone

System, PCB, & Package Design 

What's Good About ADW’s Model Management? 16.6 Has a Few New Enhancements!

New Model Management capabilities are now available in the SPB 16.6 Allegro Design…

• less than a min read
Allegro 16.6 , flow manager , 16.6 , Allegro Design Workbench , Library flow , Library and design data management , SPB , setup , design data management , design , PCB design , Grzenia , model editor , library , ADW , Allegro

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Smart Layer Behavior for Add Connect? It’s in…

When using the Add Connect command in the 16.6 Allegro PCB Editor , the active layer…

• less than a min read
PCB , Allegro 16.6 , layer stacks , PCB Editor , Layout , PCB design , Grzenia , Allegro

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Two-Layer PCB Support? Check Out 16.6!

By default, the top and bottom stackup layers do not support the placement of embedded…

• 2 min read
Allegro 16.6 , layer stacks , via , PCB design , Grzenia , Allegro PCB Editor , Allegro

Analog/Custom Design

Adding Weighted Noise Via Calculator Custom Function

Applying a weighting factor to a Noise Summary run requires lots of steps and the…

• 1 min read
Analog Design Environment , ADE XL , ADE , ViVA , Custom IC Design

Analog/Custom Design

Virtuoso Video Diary: Getting Started with the New Virtuoso ADE Product Suite

Hey, did you hear the buzz around the new Virtuoso ADE product suite , which was…

• 3 min read
Analog Design Environment , Virtuoso ADE Verifier , ADE GXL , Analog Simulation , ADE XL , ADE , Block-level simulation , Monte Carlo , Virtuoso , ADE-GXL , ADE-XL , Virtuoso Video Diary , Custom IC Design , Virtuoso ADE Explorer , Virtuoso ADE Assembler

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Advanced Flex and Rigid-Flex Design Support (Reason…

Why Rigid-Flex? For nearly all applications, customers continue to demand smaller…

• 4 min read
Allegro 17.2 , Rigid-Flex , MCAD-ECAD , PCB design , Allegro PCB Editor , IPC-2581 , Why Move Up to 17.2

Breakfast Bytes

IEDM, New This Year

It might seem a bit premature to be talking about IEDM since it isn't until December…

• 3 min read
International Electron Devices Meeting , 5nm test chip , IEDM

Breakfast Bytes

Gimme a G...Gimme a 3...Whatcha Got?...DSP

Today at the Linley Mobile and Wearables Conference in Santa Clara, Cadence is announcing…

• 2 min read
linley mobile and wearables , linley group , Fusion G3 , Linley , Tensilica , linley mobile , Tensilica Fusion G3 DSP , Breakfast Bytes

System, PCB, & Package Design 

Cadence Online Support—Empowering Learning! New Learnings—Sigrity 2016

Cadence Online Support Features Setting up ‘My Alerts” The My Alerts section displays…

• 1 min read
PCB SI , Constraint-driven PCB Design flow , PDN , Signal Intregrity , SigXP UI , PCB Signal and power integrity , Power Integrity , "PCB SI" , Signal Integrity , "PCB design" , PCB Signal integrity , Allegro PCB SI , SI analysis and modeling , power

Whiteboard Wednesdays

Whiteboard Wednesdays - Introduction to the New Tensilica Fusion G3 DSP

In this week's Whiteboard Wednesdays video, Paul Garden provides an introduction…

• less than a min read
DSP , Whiteboard Wednesdays , IP , floating point DSP , Tensilica , Tensilica IP

Breakfast Bytes

Pathfinding Beyond 5nm

One of the most interesting sessions that I attended at SEMICON West the week before…

• 4 min read
tunnel fet , IBM , carbon nanotube , semicon west , imec , coolcube , 5nm , FD-SOI , silicon nanowire

Breakfast Bytes

CDNLive India

CDNLive India is coming up on August 9th and 10th in Bengaluru. I will be there and…

• 2 min read
CDNLive India , CDNLive , bengaluru , bangalore

System, PCB, & Package Design 

Cadence Online Support—Empowering Learning! New Learnings from June 2016

Cadence Online Support Features " You might also be interested in ” Section …

• 2 min read
16.6 , PCB Signal and power integrity , "PCB design" , application note , Allegro
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