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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Digital Design

EDA Unplugged: The Behind-The-Scenes Bloopers of Chip Design

Welcome to the binge-worthy series you didn't know you needed—"EDA: Silicon, Security…

• 4 min read
videos , online courses , Electronic Design Automation , training bytes , Semiconductor , online training

Life at Cadence

Uniting Innovators: CIC 2025 Showcases Cadence’s One Team Culture

What happens when 500 Cadence employees from 22 countries come together to share…

• 6 min read
innovation , Cadence Culture

Verification

Training Insight: Unlocking the Power of the Xcelium Logic Simulator

In the fast-paced world of digital design and verification, simulation tools are…

• 1 min read
Xcelium Logic Simulator , Training Insights

Analog/Custom Design

Spectre 25.1 Release Now Available

The SPECTRE 25.1 release is now available for download at Cadence Downloads. For…

• 1 min read
featured , Spectre FMC Analysis , Spectre RF , Spectre Photonics , Spectre AMS Designer , Spectre , Spectre Fast Monte Carlo , Spectre X Simulator

Verification

Fast Emulation Requires Fast Debug! This Is How It is Done

Introduction Emulation has become a critical tool for verifying complex system-on…

• 3 min read
debug , Palladium , verisium , Emulation , Verisium Debug

Verification

Scalable I/O Virtualization: A Deep Dive into PCIe’s Next Gen Virtualization

The demands of modern cloud computing—massive scale, constant agility, and tight…

• 6 min read
Verification IP , Functional Verification , VIP , PCIe

SoC and IP

Next-Gen Memory Starts Here: Cadence at the Future of Memory and Storage

FMS: the Future of Memory and Storage is fast approaching (August 5-7 at the Santa…

• 2 min read
ddr5 , Design IP , Memory , FMS , PCIe , SerDes , UALink

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Verification

LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor…

• 4 min read
Verification IP , LOW POWER DRAM , JEDEC , LPDDR6 Vs LPDDR5 , DRAM , lpddr5 , lpddr5x , memory models , Lpddr6

Verification

UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC

As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become…

• 2 min read
Verification IP , artificial intelligence , uvm , LLR , Functional Verification , UEC , Ethernet , HPC , Ethernet UEC , AI/ML

Digital Design

Silicon Signoff and Verification 25.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 25.1 release is now available for download

• 7 min read
ECO , inter-power domain , Silicon Signoff and Verification , power-up analysis , Voltus IC Power Integrity Solution , Tempus , cell electromigration , 3D-IC , Voltus InsightAI , advanced multi-input switching , Power Analysis , 3D-IC Technology , certus , skew , Skew Modeling and Analysis , vectorless

Verification

MIPI MPHY 6.0: Enabling Next-Generation UFS Performance

High-speed chip-to-chip data transfer is continuously evolving to meet increasing…

• 1 min read
Verification IP , UniPro , MIPI Alliance , VIP , MIPI , MPHY

Corporate News

Baylor University and Olssen Optimize Data Centers with Cadence

Data center infrastructure is changing in tandem with the advancements in AI and…

• 2 min read
designed with cadence

System, PCB, & Package Design 

Discover Hidden Gems: Must-See Underrated Cadence Community PCB Design Threads

Explore hidden gems in Cadence Community Forums—underrated PCB design threads packed…

• 2 min read
PCB , community forum , PCB design , allegro x , SKILL , tcl

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

• 2 min read
Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso , Custom IC Design , Custom IC , IC design , IC23.1

Verification

Celebrating LPDDR6 Specification Publication: Cadence Hosts JEDEC LPDDR Meeting

Low-power DDR SDRAM is one of the most widely used memories in the semiconductor…

• 2 min read
Verification IP , Design IP , JEDEC , LPDDR PHY IP , DRAM , lpddr5 , LPDDR Controller IP , memory models , Lpddr6

Digital Design

Budgeting Power Like A Pro: Don't Let Your Chip Max Out Its Power Credit Limit

Power planning in chip design is a lot like managing your monthly budget. If you…

• 6 min read
Genus , low-power technique , training , Optimize , online training

SoC and IP

Designing the AI Factories: Unlocking Innovation with Intelligent IP

The rapid evolution of artificial intelligence (AI) is reshaping the technological…

• 3 min read
Design IP , IP , AI Factories , memory IP , semiconductor IP , Memory Modules , AI

Computational Fluid Dynamics

Professionals in CFD with Dr. Amalia Argyridi

In this edition of the Professionals in CFD series, we are happy to feature Dr. Amalia…

• 5 min read
Beta CAE , Computational Fluid Dynamics , WomenAtCadence , women in engineering , Women in CFD
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