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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Designing a PCB in Harmony with Your 3D Extraction Expert

You know who we are talking about. The guy in the corner with all the PhDs hanging…

• 1 min read
SI , 3D EM , High Speed Structure Optimization , 3D EM HSSO , 3D EM High Speed Structure Optimizer , Signal Integrity , 3D , HSSO , Sigrity , System Serial Link , Allegro

Verification

App Note Spotlight: Streamline Your SystemVerilog Code, Part II - SystemVerilog …

Welcome back to a special multi-part edition of the App Note Spotlight, where we…

• 2 min read
performance , SystemVerilog , Functional Verification , xcelium simulator

Breakfast Bytes

TI Flies Pegasus in the Clouds

Kyle Peavy of Texas Instruments reported on their experience with Pegasus, Cadence…

• 5 min read
Physical verification , CDNLive , pegasus , cloud , Texas Instruments

Breakfast Bytes

Samsung Foundry Forum: 10, 8, 7, EUV, 5, 4, GAA, 3...

Last week was the Samsung Foundry Forum. Almost exactly a year ago, Samsung reorganized…

• 13 min read
3nm , Samsung , gaa , samsung foundry forum , sff , 5nm , 7nm , EUV

Verification

Empowering Generation - Range Generated Fields (RGF)

Specman constraints solver process consists of a series of reductions and assignments…

• 8 min read
Specman , Specman/e , Generation , e language , Constraints

Analog/Custom Design

Virtuosity: How to Run a Multi-Technology Simulation (MTS)?

Are you looking for some hands-on experience with running multi-technology simulation…

• 3 min read
ADE Explorer , Explorer , Rapid Adoption Kit , Virtuoso , Spectre , ADE-XL , Virtuosity , Custom IC Design , Assembler , ADE Assembler

Breakfast Bytes

It'll be HOT on Sunday Evening at DAC

For several DACs now, Heart of Technology (HOT) has run a party on Monday night.…

• 2 min read
DAC , HOT , Heart of Technology , Gary Smith , sjsu

Breakfast Bytes

7 Ways to Get the Most out of DAC

DAC, the Design Automation Conference, is coming up. It's Sunday June 24th to Thursday…

• 7 min read
DAC , dac2018 , 55DAC

Whiteboard Wednesdays

Whiteboard Wednesdays - The Advantages and Trade-offs of HBM2 and GDDR6

In this week’s Whiteboard Wednesday, Marc Greenberg discusses the advantages and…

• less than a min read
Whiteboard Wednesdays , Memory , HBM

Breakfast Bytes

If It's Tuesday This Must Be Belgium. My First Visit to imec

Outside of semiconductor, Belgium is famous for three things: beer, chocolate, and…

• 6 min read
Memory , 3D NAND , imec , DRAM , RRAM , belgium , MRAM , EUV , DTCO

Breakfast Bytes

Aren't All Crosswords Cryptic?

It's Memorial Day, so Breakfast Bytes is off today. Well, obviously not completely…

• 3 min read
off-topic , crossword

Analog/Custom Design

Virtuoso Video Diary: Bridging Virtuoso and Mixed-Signal Simulation Tools Using …

Cadence has introduced Command-Line IP Selector (CLIPS) support to provide a bridge…

• 2 min read
custom/analog , Mixed-Signal , Virtuoso , Virtuosity , Virtuoso Video Diary , Custom IC Design

Academic Network

Academic Network at VLSI-DAT Symposium in Taiwan 2018

2018 was the second year Cadence Academic Network supported the VLSI-DAT Symposium…

• 1 min read
VLSI , university , Taiwan , Cadence Academic Network , academia

Breakfast Bytes

GDPR Starts Today

You are probably subscribed to a number of email newsletters. No doubt you have been…

• 6 min read
Facebook , gdpr

Breakfast Bytes

Embedded Vision: Seeing 20,000X Improvement

This week it is the Embedded Vision Summit in Santa Clara. Over the last few years…

• 6 min read
Embedded Vision Summit , Tensilica , neural network

Breakfast Bytes

What's For Breakfast? Video Preview May 28th to June 1st 2018

https://youtu.be/UEAZjA-_xrE Coming from Embedded Vision Summit (camera Sean)…

• less than a min read
DAC , pegasus , HOT , Heart of Technology , imec , 55DAC

Breakfast Bytes

MEMS Design Competition: The Envelope Please...

The Cadence Academic Network sponsored a MEMS design contest over the last couple…

• 3 min read
Cadence Academic Network , CDNLive , MEMS

Whiteboard Wednesdays

Whiteboard Wednesdays - The Truth about Designing for Automotive Functional Safe…

In this week’s Whiteboard Wednesday, Tom Hackett challenges conventional wisdom and…

• less than a min read
Automotive , Whiteboard Wednesdays , functional safety , automotive IP , ISO 26262 , ADAS

Breakfast Bytes

Accelerating AI: ...Present and Future

Yesterday I wrote about the first part of Krste Asanović's presentation Accelerating…

• 5 min read
artificial intelligence , risc-v , Krste Asanović , sifive
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