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Featured

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
Cadence Japan 15 Dec 2025 • less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
Corporate 11 Dec 2025 • 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP(Verification IP:VIP)を発表しました。今回発表されたVIPは…

Cadence Japan
Cadence Japan 4 Dec 2025 • less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
Cadence Japan 1 Dec 2025 • 2 min read
featured , japanese blog
cdns - all_blogs_categories

  • All 6183
  • Corporate News 220
  • Life at Cadence 202
  • Academic Network 167
  • Analog/Custom Design 780
  • Artificial Intelligence 24
  • Cloud 21
  • Computational Fluid Dynamics 367
  • Data Center 41
  • Digital Design 437
  • Learning and Support 56
  • RF Engineering 114
  • SoC and IP 419
  • System, PCB, & Package Design  999
  • Verification 1300
  • Cadence Japan 8

  • CFD(数値流体力学) 45
  • 中文技术专区 15
  • カスタムIC/ミックスシグナル 192
  • PCB、IC封装:设计与仿真分析 136
  • PCB解析/ICパッケージ解析 44
  • PCB設計/ICパッケージ設計 61
  • RF /マイクロ波設計 44
  • Spotlight Taiwan 61
  • The India Circuit 91
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

Breakfast Bytes

Jasper User Group Preview

I have been going to the Jasper User Group for years. Before Cadence acquired Jasper…

Paul McLellan 2 Nov 2021 • 1 min read
Jasper User Group , JUG , formal , JasperGold , verification

RF /マイクロ波設計

マイクロ波製品ダイジェスト(MPD)の記事でAWR Design Environment V16ソフトウェアを紹介

5G無線システムと接続されるデバイスは、今日、考えられるすべての業界で急増しています。運転技術のリーダーは、性能、サイズ、およびコストによって定義および差別化されたRF対応の製品の市場機会を活用しています…

RF Design Japan 2 Nov 2021 • less than a min read
5G , Virtuoso RF Designer , AWR Design Environment , awr , Multiphysics analysis , RF design , AWR Media Alert , japanese blog , Allegro PCB Designer , IC design , Wireless Communication

RF Engineering

Cadence AWR Design Environment Empowers RF/Microwave System Design

Microwave Product Digest (MPD) Article Features AWR Design Environment V16 Software…

TeamAWR 1 Nov 2021 • 1 min read
5G , Virtuoso RF Designer , AWR Design Environment , awr , Multiphysics analysis , RF design , AWR Media Alert , Allegro PCB Designer , IC design , Wireless Communication

Breakfast Bytes

Designing Planet-Scale Video Chips on Google Cloud

In the last couple of months, I have attended two presentations about Google's video…

Paul McLellan 1 Nov 2021 • 4 min read
google cloud , google

Breakfast Bytes

Sunday Brunch Video for 31st October 2021

https://youtu.be/GuGgaH72-6U Made at Calistoga in Napa CA (camera Carey Guo) Monday…

Paul McLellan 31 Oct 2021 • less than a min read
sunday brunch

Computational Fluid Dynamics

This Week in CFD

Despite this being the Halloween time of year, this week's roundup of CFD news isn…

John Chawner 29 Oct 2021 • less than a min read
CFD , Pointwise , Computational Fluid Dynamics , Mesh Generation , Omnis

System, PCB, & Package Design 

IC Packagers: Module Support in IC Package Design

It is quite common to reuse memory stacks across designs. These memory stacks are…

avijeet 28 Oct 2021 • 2 min read
APD , IC Packaging & SiP design , IC Packagers , Allegro Package Designer , 17.4-2019

Verification

Why is Ethernet Time-sensitive Networking (TSN) Adaptation So Rapid in the Automotive…

At a particular point in time, the automotive industry continued to add more and…

Krunal Patel 28 Oct 2021 • 1 min read
Automotive , Verification IP , SoC verification , IP verification , Ethernet VIP , Functional Verification , VIP , Ethernet standards , Automotive Ethernet , TSN

Breakfast Bytes

Always Listening, HiFi 1 DSP

Today, at the Linley Processor Conference, we announced the latest addition to the…

Paul McLellan 28 Oct 2021 • 4 min read
always on , audio , hifi 1 , Tensilica , hifi 1 dsp , earbuds

Life at Cadence

My Life at Cadence: Guillaume Foix

Cadence was recently ranked #7 on Newsweek’s Most Loved Workplaces list for 2021…

Lautanen 27 Oct 2021 • 1 min read
Insights on Culture , Culture , cadence , GPTW , my life at cadence , life at cadence , cadence emea

Breakfast Bytes

October Update: GPTW, Intel Fabs, Apple, and More

These monthly updates normally occur on the last Friday of the month, but that is…

Paul McLellan 27 Oct 2021 • 5 min read
Intel , Apple , semi , Arteris , apple m1

カスタムIC/ミックスシグナル

Virtuoso Meets Maxwell: EMX Planar 3D Solverでのメッシュの表示

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

Custom IC Japan 26 Oct 2021 • less than a min read
Virtuoso 3D Viewer , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Layers Assistant , EMX Models , Electromagnetic analysis , Virtuoso , EMX , japanese blog , Custom IC Design , EMX Solver , Virtuoso Layout Suite , Custom IC , 3D Mesh

System, PCB, & Package Design 

BoardSurfers: Training Insights: Manually Placing Components in Allegro PCB Edit…

Component placement is one of the most critical aspects of PCB designing. As the…

Taanya 26 Oct 2021 • 4 min read
BoardSurfers , 17.4-2019 , PCB design , Training Insights , Allegro PCB Editor , Allegro

定制IC芯片设计

Virtuoso Meets Maxwell:通过库实现系统分析和物理实现

欢迎阅读这篇博文了解如何创建组件和padstack库,以用于以Virtuoso 平台为驱动的多工艺流程。本文所描述的工具类似图书管理员的工作,它们必须通过各种途径来组装组件IP…

Guru Rao 26 Oct 2021 • 1 min read
Technology Independent Layout Pcell , Unified Library , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Virtuoso MultiTech , Electromagnetic analysis , librarian , SiP Layout Option , ICADVM20.1 , Cadence SiP Layout , TILP , Chinese blogs , VMM

Breakfast Bytes

TSMC OIP: 3DFabric and Integrity 3D-IC

Today is TSMC's OIP (or, to give it its full name, TSMC 2021 Online OIP Ecosystem…

Paul McLellan 26 Oct 2021 • 3 min read
OIP , Integrity , TSMC , Innovus , integrity 3d-ic , 3dfabric

CFD(数値流体力学)

計算機航空宇宙とCFDの進化

初めに翼がありました。具体的には、1968年に超臨界の翼および翼を設計するために何か新しいものが必要であることが明らかになりました。今日では、シミュレーションによる航空機認証や…

CFD Japan 25 Oct 2021 • 1 min read
CFD , Aerospace , FLO22 , Pointwise , Computational Fluid Dynamics , CFD Applications , NUMECA , japanese blog , Mesh Generation

CFD(数値流体力学)

クワッドコプタードローンの飛行時間と航続距離の延長にOMNIS を活用

ドローンは、軍事、産業、個人消費者の領域において、幅広い用途での効率的なソリューションであることが証明されています。過去10年間でドローンの利用は急増しており、その年間成長率は50…

CFD Japan 25 Oct 2021 • less than a min read
CFD , Computational Fluid Dynamics , NUMECA , japanese blog

RF /マイクロ波設計

μWaveRiders:Cadence AWR Design Environment/プロジェクトブラウザのヒントとコツ

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design…

RF Design Japan 25 Oct 2021 • 1 min read
microwave , RF Simulation , Circuit simulation , AWR Design Environment , awr , Tips/Tricks , RF design , japanese blog , Visual System Simulator(VSS)

Analog/Custom Design

Virtuoso ICADVM20.1 ISR21 and IC6.1.8 ISR21 Now Available

The ICADVM20.1 ISR21 and IC6.1.8 ISR21 production releases are now available for…

Virtuoso Release Team 25 Oct 2021 • 3 min read
Cadence blogs , ADE Explorer , IC Release , Announcement blog , Virtuoso RF Solution , Virtuoso , ICADVM20.1 , IC Release Blog , Custom IC Design , Custom IC , IC design , IC6.1.8 , Analog IC Design , ADE Assembler
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CDNS - Fix Layout Hompage

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