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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

IEDM 2020 Preview

Every December is the IEEE International Electron Devices Meeting (IEDM). The somewhat…

• 5 min read
iedm 2020 , IEDM

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: Virtuoso RF Solutionのクイックスタート

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Rapid Adoption Kit , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Layout EXL , Virtuoso MultiTech , ICADVM20.1 , Cadence SiP Layout , japanese blog , Custom IC Design , RAKs , Allegro , VMM

System, PCB, & Package Design 

IC Packagers: Why You Can’t Start a Co-Design Die in Allegro Package Designer

Let’s investigate this question today, as I’ve been asked a few times over the years…

• 4 min read
IC Packaging & SiP design , Allegro Package Designer , 17.4-2019

Analog/Custom Design

Virtuosity: Decoding the Mechanics of What If in Voltus-Fi-XL

What if you could foresee potential changes in your design and analyze their impact…

• 4 min read
EMIR Analysis , debug , Voltus-Fi-XL , what-if analysis , Virtuoso , Virtuosity , ICADVM20.1 , Custom IC Design , IC6.1.8 , EMIR

Breakfast Bytes

WEAA EDA/IP Product of the Year: Digital Full Flow with iSpatial Technology

Aspencore Media, the publishing house that owns EDN (where I first started blogging…

• 3 min read
EDN , EETimes , digital full flow , aspencore media , ispatial

カスタムIC／ミックスシグナル

Start Your Engines: AMS Designerのローパワー・ミックスシグナル・シミュレーションにおける２つの重要なコンポーネント

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• less than a min read
AMS Designer , mixed-signal simulation , Mixed-Signal , low-power design , Connect Module , japanese blog , low power format

Breakfast Bytes

Cadence 5th Annual Photonics Event

Coming up on December 1 - 3 is the 5th annual Cadence Photonics event, although it…

• 2 min read
HPC , photonics

Breakfast Bytes

Cadence Cloud: The Video Version

Recently, Cadence released a series of videos about all the various aspects of Cadence…

• 2 min read
cloudburst , cadence cloud

カスタムIC／ミックスシグナル

Virtuosity:Cadence Learning and Supportポータルの最新情報 – パート 1

この数か月間の状況において、私たちは皆、新しい活動に熱中し、新しいことを学び、日常生活に何か興味のあることを加えています。 似たような路線で、 Cadence Learning…

• less than a min read
RAK series , Custom IC Design flow , Virtuoso Analog Design Environment , Virtuoso , japanese blog , CIC flow , Custom IC Design , RAKs , Virtuoso Layout Suite , Custom IC

Analog/Custom Design

Virtuosity: Conserve Power— Running In-Design Checks

Today’s blog focuses on in-design checks that offer an easy and convenient way to…

• 6 min read
In-Design Checks , Low Power , virtuoso power manager , Schematic XL , in-design , VPM , Schematic Editor , ICADVM20.1 , UPF , Power Manager , mixed signal , Liberty , Custom IC Design

Breakfast Bytes

Formal Verification Signoff for Digital IP

At the recent Jasper User Group meeting, one of the presentations was by David Vincenzoni…

• 3 min read
Jasper User Group , JUG , formal , ST Microelectronics , JasperGold

Verification

Training Insights - Still Relying on Static-Only CDC Signoff? Introducing the JasperGold…

RTL designers are creating increasingly complex designs, and are under relentless…

• 3 min read
Functional Verification , clock domain crossings , CDC , RDC , JasperGold , Superlint , Reset , Formal verification

Breakfast Bytes

Arm Goes for It

At the recent Linley Processor Conference, Arm presented two processors. This was…

• 5 min read
cortex-a78 , cortex-x1 , ARM

Life at Cadence

Think Beyond the Chip

Cadence is certainly well-known for our design tools for integrated circuit (IC)…

• 4 min read
3D-IC , moore's law

Verification

Have You Ever Wanted to Learn Specman/e and Did Not Know How?

As a verification engineer, you want your toolbox to be varied and rich. It looks…

• 1 min read
Specman , Specman/e , Functional Verification , hvl

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: チップにとらわれない – ICとICパッケージ設計および検証ツール間におけるクラス最高の相互運用性の優位点

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
IC Packaging , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso Analog Design Environment , Virtuoso , Spectre , mixed signal , japanese blog , Custom IC Design , Allegro

System, PCB, & Package Design 

BoardSurfers: Training Insights: RF PCB Design Flow Using Allegro Editors

Allegro® RF PCB solution provides you with a unified design solution for complex…

• 5 min read
17.4 , RF PCB , Cadence Online Support , 17.4-2019 , Allegro PCB Editor , Allegro

Digital Design

Voltus Voice: Amplifying Your Chip Performance and Reliability to Solve Big-Data…

This blog introduces the new cloud-ready Extensively Parallel (XP) solution from…

• 5 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Multi-Physics Technology , Power Integrity , cloud , parallel processing , distributed processing

System, PCB, & Package Design 

IC Packagers: Key Functions for Good SKILL Programming in Allegro Package Design…

Many of you out there are SKILL coders (or have these people on your team). SKILL…

• 6 min read
17.4 , IC Packaging & SiP design , Allegro Package Designer , 17.4-2019
CDNS - Fix Layout Hompage