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Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
KomalJohar 17 Dec 2025 • 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
Corporate 17 Dec 2025 • 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
Cadence Japan 15 Dec 2025 • less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
Corporate 11 Dec 2025 • 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
cdns - all_blogs_categories

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  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

SoC and IP

USB 3.2—The USB Type-C Connector Finally Met its Match

It’s only a week before the first event of USB Developer Days , a series of meetings…

Jacek Duda 19 Sep 2017 • 1 min read
USB 3.0 , USB Type-C , DisplayPort , USB , USB 3.2 , power delivery , USB 3.1

Breakfast Bytes

CDNLive India 2017 Trip Report

I went to Bangalore to CDNLive India. It has a different structure from the other…

Paul McLellan 19 Sep 2017 • 6 min read
ml , CDNLive India , dl , CDNLive , machinelearningdeeplearning , AI , Breakfast Bytes

Analog/Custom Design

Virtuosity: Sweeping Multiple Config Views

Before IC6.1.7 ISR10, you could sweep multiple views in ADE for only one block in…

Arja H 18 Sep 2017 • 2 min read
Analog Design Environment , ADE Explorer , Explorer , Analog Simulation , ADE , Virtuoso Analog Design Environment , Analog Design Environment , Schematic Editor , Virtuosity , Circuit Design , Custom IC Design , Schematic , ADE Assembler

System, PCB, & Package Design 

Follow Video-Embedded Troubleshooting Articles for Easier Debugging and Empowered…

Finding a way out of situations is routine in today’s ever changing world—more so…

Jasmine 18 Sep 2017 • 2 min read
PCB , AMS simulator , OrCAD Capture , Allegro

Breakfast Bytes

Legato: Smooth Memory Design

At CDNLive in Bengaluru (fka Bangalore), Cadence announced the Legato solution for…

Paul McLellan 18 Sep 2017 • 4 min read

Analog/Custom Design

Virtuosity: What Color is Your Virtuoso Wearing Today?

Like you, Virtuoso can dress in a different color too every day. Interested to know…

Rishu Misri Jaggi 15 Sep 2017 • 3 min read
Customize Virtuoso , Virtuoso Editor , color , color-aware design , Virtuosity , Custom IC

Breakfast Bytes

TSMC Process Roadmap Update

This Wednesday was TSMC's OIP Ecosystem Forum, one of two major events that TSMC…

Paul McLellan 15 Sep 2017 • 5 min read
22_ULP , 22_ULL , 7nm+ , 12FFC , TSMC , 16FFC , 28HPC+ , 7nm , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview September 18th to 22nd 2017

https://youtu.be/mrUIXwMuNy8 Coming from TSMC OIP Symposium, Santa Clara (camera…

Paul McLellan 14 Sep 2017 • less than a min read
legato , CDNLive , hong kong , neural nets , India , Singapore

Breakfast Bytes

Why Are Design Tools So Bad? Or Are They?

In a recent feature article at Electronic Engineering Journal, Kevin Morris asks…

Paul McLellan 14 Sep 2017 • 6 min read
electronic engineering journal , bugs , EDA , design tools

The India Circuit

CDNLive India Keynote: Qualcomm On 5G And More

CDNLive India concluded last Friday and what an event it was! With 87 paper presentations…

Madhavi Rao 13 Sep 2017 • 4 min read
5G , artificial intelligence , CDNLive India , CDNLive , IoT , machine learning , Qualcomm , mobile , 7nm

Breakfast Bytes

New Cadence Support of TSMC 7nm, 7nm+, and 12FFC

A quick guide to TSMC processes. There is a 10nm process but very little development…

Paul McLellan 13 Sep 2017 • 4 min read
OIP , 7nm+ , 12FFC , TSMC , DDR , 7nm , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Benchmarking Deep Learning Platforms: The Results

In this week's Whiteboard Wednesdays video, Mengjun Leng follows up on last week…

References4U 12 Sep 2017 • less than a min read
Whiteboard Wednesdays , deep learning

SoC and IP

Cadence IP Is Great for Automotive

If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision…

PaulaJones 12 Sep 2017 • less than a min read
USB 3.0 , Design IP , DDR4 , LPDDR4 , PCI Express 3.0 , LPDDR , IP blocks , PCIe Gen4 , MIPI , DisplayPort , Automotive Ethernet , USB , memory IP , Ethernet , PCIe , 16nm , PCIe Gen3 , imaging , Ethernet PHYs , PCI

Verification

How to Get to a Trillion Devices in the Internet of Things in 2035

Next month at Arm TechCon, one of the key discussion topics with be the internet…

fschirrmeister 12 Sep 2017 • 4 min read
prototyping , cadence , palladium z1 , IoT , Socrates , Emulation , Internet of Things , ARM , protium s1 , verification

Analog/Custom Design

Virtuosity: Driving Along a Longer Route May Take You Home Sooner!

On my way back home every day, I need to make a decision — should I drive less, or…

Rishu Misri Jaggi 12 Sep 2017 • 4 min read
library manager , Virtuoso , Virtuosity , physConfig , CPH , copy library , Custom IC

Breakfast Bytes

Automotive IP Family for TSMC 16FFC

At the semiconductor level, automotive poses huge challenges due to an experience…

Paul McLellan 12 Sep 2017 • 3 min read
OIP , tsmc 9000A , TSMC , renasas , Ethernet , PCIe , semiconductor IP , DDR , Breakfast Bytes

Digital Design

Why Pegasus Is the Biggest Breakthrough in SoC Physical Verification in 20 Years…

These days, DRC rule deck availability for the market tools is not a major issue…

Manoj Chacko 11 Sep 2017 • 3 min read
Physical verification , massively scalable , pegasus , DRC , Cloud ready

Breakfast Bytes

Xilinx/Arm/Cadence/TSMC Announce World's First 7nm CCIX Silicon Demonstrator; and…

"It takes a village to raise a child," as the African proverb says. It seems to take…

Paul McLellan 11 Sep 2017 • 3 min read
ARM Techcon , cadence , ccix , TSMC , accelerator , xilinx , 7nm , Breakfast Bytes , FPGA

Breakfast Bytes

CDNLive Boston Keynotes

There were three keynotes to kick off CDNLive Boston. Tom Beckley gave the Cadence…

Paul McLellan 8 Sep 2017 • 8 min read
Automotive , Tom Beckley , Protium , Palladium , silicon photonics , ADAS , Medtronic , Breakfast Bytes
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