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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Analog/Custom Design

Virtuosity: What's New in Run Plan – Part III

After two interesting blogs by Yagya Mishra that explained the most popular features…

• 3 min read
Analog Design Environment , ICADVM18.1 , Rapid Adoption Kit , ADE , worst case corners , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , Run Plan , Custom IC Design , RAKs , IC6.1.8 , ADE Assembler

定制IC芯片设计

Virtuoso视频日记：这根线是怎样连接的？

Virtuoso Schematic Editor L 的Probes工具是连接辅助工具，能满足您识别已存在的连接关系，过滤这些连接关系，并且将探测路径信息存为CSV文件…

• less than a min read
Chinese blog , Virtuoso Schematic Editor , Virtuoso Video Diary , Probes assistant , Net Connections , Custom IC Design

Breakfast Bytes

IEDM: EUV, the Road to HVM and Beyond

At IEDM in December, the Sunday preceding the conference proper consists of two short…

• 8 min read
asml , EUV , IEDM

Breakfast Bytes

AlphaZero: Four Hours to World Class from a Standing Start

Last year I wrote about AlphaZero in my post Deep Blue, AlphaGo, and AlphaZero .…

• 7 min read
deep learning , alphazero , go , AI , stockfish , chess

System, PCB, & Package Design 

DesignCon 2019: Is this the Year?

2019 has started --- is this the year of advanced packaging, where system design…

• 1 min read
DesignCon , packaging

Verification

Verification of ML IP and Specman—Our Hackathon Project

If you are lucky enough and your company spends a few working days each year on a…

• 7 min read
ml , Specman , Specman/e , Specman e , machine learning , specman elite , verification coverage , verification

Breakfast Bytes

AMD Keynote at CES

As I said in my post about CES last week (see my post Consumer Electronics: 5G, AI…

• 9 min read
Lisa Su , CES , AMD

Breakfast Bytes

Tensilica at CES

Tensilica has been attending CES for many years, before it was acquired by Cadence…

• 3 min read
hifi 5 , CES , Vision P6 , Tensilica , dna100

Analog/Custom Design

Accurate Pin-to-Pin Resistance Modeling for Wide, Slotted Metal Structures Using…

In Analog/RF layouts, designers frequently use slotted metal structures. Such slotting…

• 3 min read
Extraction , Quantus

Breakfast Bytes

Gordon Moore Killed the Oakland Tribune

The Oakland Tribune closed down in 2016. It remains to be seen if the San Jose Mercury…

• 7 min read
newspapers , journalism

Breakfast Bytes

Consumer Electronics: 5G, AI, and Air Taxis

I'm sure you've heard the great marketing catchphrase that "What happens in Vegas…

• 5 min read
Apple , Consumer Electronics , CES , ces2019

Analog/Custom Design

Virtuosity: Saving Time, Effort, and Money with Express Pcells

Use the Express Pcell feature and see for yourself how you can save time, effort…

• 3 min read
Advanced Node , Express Pcell , pcell , Virtuoso , Virtuosity , Layout design , Custom IC Design , Virtuoso Layout Suite , Parameterized Cell , Custom IC , Layout Editing

Breakfast Bytes

SiFive: The Magnificent Seven

At least for now, I think that the most significant of the RISC-V processor companies…

• 7 min read
risc-v , ARM , sifive

Breakfast Bytes

Breakfast Nibbles: Predictions for 2019

It is the start of the year, so time to provide my predictions for 2019. These are…

• 5 min read
5G , Automotive , China , Memory , deep learning , 3nm , cloud , DRAM , 5nm , neural networks , EUV

Breakfast Bytes

2018: A Year of Breakfasts

It's the start of a new year. Tomorrow, I'll pick out what I think that the big trends…

• 5 min read
security , Automotive , artificial intelligence , China , deep learning , photonics , 5nm , EUV

Breakfast Bytes

Sunday Brunch Video for 8th January 2019

https://youtu.be/tAMYvJJcPy0 Made at Vieira Park, San Jose (camera Carey Guo) Wednesday…

• less than a min read
interconnect , risc-v , esperanto , ruthenium , maxion , swerv , IEDM

Breakfast Bytes

RISC-V Cores: SweRV and ET-Maxion

December was the first RISC-V summit at the Santa Clara Convention Center. I covered…

• 6 min read
Western Digital , risc-v , esperanto , maxion , swerv

Digital Design

Glitch Noise Analysis and Fixing with Tempus

Every design engineer knows something about glitch but for many the details are a…

• 5 min read
SI , Tempus , STA , delay , noise , glitch , Signal Integrity , crosstalk , signoff , silicon signoff , Sign off , timing

Breakfast Bytes

IEDM: The World After Copper

I remember Gary Patton, the CTO of GLOBALFOUNDRIES, telling me once that research…

• 9 min read
interconnect , cobalt , copper , 3nm , contact , imec , amat , 5nm , IEDM , rubidium
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