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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Spotlight Taiwan

Cadence一舉囊括亞洲金選獎(EE Awards)五項大獎!

由電子工程領域專業媒體《EE Times》及《EDN》出版集團ASPENCORE台灣/亞洲團隊主辦之第二屆亞洲金選獎(EE Awards Asia)在12月8日盛大圓滿落幕…

• less than a min read
Taiwan , system analysis , taiwanese blog , intelligent system design , integrity3DIC

Verification

Demonstrating PCIe 6.0 Equalization Procedure

The Link equalization procedure enables components to adjust the Transmitter and…

• 4 min read

Computational Fluid Dynamics

Last Week at Fidelity CFD

Let's take one last look during 2022 of what's happening here at Fidelity CFD. From…

• 3 min read
CFD , Marine Engineering , FINE Marine , turbomachinery , Pointwise , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , cadencelive , Mesh Generation

Life at Cadence

Accelerating the Move to Society 5.0

Our world has gone through many transformations, and technology is accelerating these…

• 3 min read
Industry 4.0 , society 5.0 , intelligent system design

Breakfast Bytes

IEDM Keynote: Ann Kelleher on Future Technology

IEDM 2022 celebrated 75 Years of the Transistor. I wrote about it myself in my post…

• 4 min read
Intel , featured , IEDM , iedm 2022

Computational Fluid Dynamics

Adhering to User Preferences with Entity Selection

It is often a cumbersome task to select the entities that ought to be modified individually…

• 4 min read
CFD , user preferences , Meshing Monday , engineering , simulation software , entity selection , Mesh Generation , Cadence CFD , Fidelity Pointwise

Verification

SD Host Controller for SD Card Verification

SD Host Controller was introduced to transfer data to SD Card from system memory…

• 2 min read
Verification IP , host , Memory , VIP , SD

RF /マイクロ波設計

μWaveRiders:成功するAWR Design Environmentでの設計 - レイアウトと部品ライブラリ

When starting a new design, it's important to take the time to consider design recommendations…

• 1 min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , Component library , Layout , microwave office , japanese blog , Visual System Simulator(VSS)

Breakfast Bytes

Sunday Brunch Video for 18th December 2022

https://youtu.be/fvfpclonVzo Made at Deer Hollow Farm (camera Carey) Monday: ChatGPT…

• less than a min read
sunday brunch

RF Engineering

μWaveRiders: Setting Up a Successful AWR Design Environment Design - Layout and Component…

When starting a new design, it's important to take the time to consider design recommendations…

• 8 min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , Component library , Layout , microwave office , Visual System Simulator (VSS)

Digital Design

Training Insights - RTL-to-GDSII Lab: Just One Click to Increase Your Confidence…

Are you struggling to run the RTL2GDSII labs? Want to speed up your learning time…

• 3 min read
Physical verification , ECO , conformal , IMC , Static timing analysis , DFT , Silicon Signoff and Verification , Genus , hold , rail analysis , Tempus , Routing , ASIC flow , LEC , drv , STA , Setup and Hold Analysis , Floorplanning , RTL-to-GDSII , Logic Design , coverage analysis , xrun , setup , logic equivalence checking , digital implementation , GDSII export , Innovus , digital full flow , physical design , Timing analysis , rtl2gds2 , Power Analysis , xcelium , CTS , RTL2GDSII , Synthesis , Placement , Tempus Timing Signoff Solution , IR drop , physical implementation

Breakfast Bytes

Photonics: Riding the Waves

Coming up on January 11th is our annual photonics event. This year it is called CadenceCONNECT…

• 4 min read
Lumerical , silicon photonics , photonics

Analog/Custom Design

Virtuosity: Annotating Scalar Outputs for Single-Point Simulation in Virtuoso Visualization…

Can scalar outputs for single-point simulation be annotated in the graph window of…

• 3 min read
annotation , Scalar Outputs Annotation , ADE Explorer , Summary Label , Virtuoso Visualization and Analysis XL , Virtuoso Analog Design Environment , ViVA , Virtuosity , Single Point Simulation , ISR26 , Scalar Ouputs , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler

System, PCB, & Package Design 

Ascent: Training Insights: Controlling Design Versions in Allegro System Capture

The Version Control feature in Allegro® System Capture lets you track every modification…

• 4 min read
PCB , System Capture , 17.4 , 17.4-2019 , Training Insights , Allegro System Capture , ASCENT , Allegro

Life at Cadence

EV Maritime Is Creating Better Boats for a Better World

EV Maritime is a New Zealand-based marine technology business, decarbonizing the…

• 1 min read
CFD , designed with cadence

Breakfast Bytes

RISC-V Summit 2022

The RISC-V Summit took place in December. It was in person and virtual. Clearly,…

• 3 min read
risc-v , risc-v summit , walden international , risc-v foundation , Qualcomm , calista redmond

Life at Cadence

Words and Their Impact on Diversity, Equity, and Inclusion

An employee's perspective about diversity, equity, and inclusion: The Words Matter…

• 4 min read
Insights on Culture , inclusion , Technical Communications , GPTW , my life at cadence , WomenAtCadence , diversity , returnship , wordsmatterinitiative , inclusivelanguage , equity

Breakfast Bytes

CES 2023 Preview: Come and See Us in the Venetian

It's nearly a New Year, and as usual, CES (what used to be called the Consumer Electronics…

• 3 min read
Consumer Electronics Show , tensilica dsp , CES , Tensilica

Analog/Custom Design

Knowledge Booster Training Bytes - How to Model Analog Blocks with Verilog-AMS Wreal…

Do you know you can speed up analog or mixed-signal simulations with digital mixed…

• 9 min read
real number modeling , AMS , AMS Designer , training , DMS , training bytes , Spectre , RNM , AMS simulation , xcelium , Modeling , wreal , Custom IC Design , wreal Model , AMS Verification , vams
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