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Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die
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Blog - Post List

Latest blogs

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由之5：如何进行“叠层设计”？

在这我们谈论的不是您的叠层设计跟其他人比怎么样，而是您设计的PCB层叠结构，是刚性板、柔性板、刚柔板，或者使用了镶嵌技术。层叠的定义，更具体而准确的层叠的定义，是至关重要的…

• less than a min read
PCB , Chinese blog , 布线 , PCB设计 , 中文 , MCAD-ECAD , Allegro PCB Editor , Allegro PCB编辑器 , 刚柔结合设计 , Allegro升级17.2 , 刚柔结合 , Allegro

Breakfast Bytes

Jaswinder's Only Job Interview

On Labor day, I didn't get the day off since I was in Delhi. I had to labor, not…

• 6 min read
bengaluru , Cadence India , Noida

Breakfast Bytes

What's For Breakfast? Video Preview September 24th to 28th 2018

https://youtu.be/NYsYkQzZADo Coming from SAP Center, San Jose (camera Sean) Monday…

• less than a min read
National Instruments , GTC , Kaufman Award , EDPS , RF design , Invecas , GlobalFoundries , esd alliance

Breakfast Bytes

Samsung Galaxy S9's Application Processor

At this year's HOT CHIPS, Jeff Rupley of Samsung presented the application processor…

• 5 min read
Samsung , m3 , 10nm , galaxy

Breakfast Bytes

The New Tensilica DNA 100 Deep Neural-network Accelerator

Today, at the beautiful Tegernsee resort outside Munich in Germany, Cadence announced…

• 6 min read
xnnc , android neural networks , dna 100 , caffe , TensorFlow , Tensilica , neural network

Whiteboard Wednesdays

Whiteboard Wednesdays - Standalone AI Processor: Tensilica DNA 100 Processor IP for…

In this week's Whiteboard Wednesdays episode, Megha Daga describes the new Tensilica…

• less than a min read
Whiteboard Wednesdays , dna 100 , AI

PCB、IC封装：设计与仿真分析

为什么电源完整性(PI)是个“热”话题——如何进行电/热协同仿真

在设计新一代产品时，我们共同追求的目标都是“更快，更小，更便宜”。然而当这与更长的电池寿命和更低的功耗要求相遇时，就向我们提出了艰巨的设计挑战。唯一可以肯定的是…

• less than a min read
PCB , 热 , PI , Chinese blog , 电源完整性 , 电热协同仿真 , Power Integrity , PCB设计 , 中文 , Sigrity , PowerDC

Breakfast Bytes

HOT CHIPS: Some HOT Deep Learning Processors

If there was a theme running through the recent HOT CHIPS conference in Cupertino…

• 5 min read
Intel , deep learning , processor , NVIDIA , machine learning , hot chips , ARM

Breakfast Bytes

CDNLive India: Asynchronous Design

Every few years the idea of doing completely clockless design gets proposed again…

• 5 min read
CDNLive India , jasper gold , Texas Instruments , Formal verification

PCB、IC封装：设计与仿真分析

三维建模与电磁场分析新工具——3D Workbench

在Cadence公司刚刚发布的Sigrity 2018版本中，介绍了全新的三维建模与电磁场仿真工具——3D Workbench。它具有当前市场上主流3D CAD…

• 1 min read
Chinese blog , 电源完整性 , 3D Workbench , 3D EM , PCB设计 , 中文 , PowerSI 3D EM , 3D CAD , Sigrity , 信号完整性 , Sigrity最新版

Breakfast Bytes

Intel's Cascade Lake: Deep Learning, Spectre/Meltdown, Storage Class Memory

At the recent HOT CHIPS in Cupertino, Sujal Vora of Intel gave a look inside the…

• 4 min read
Intel , meltdown , cascade lake , deep learning , storage class memory , optane , Spectre , 3dxpoint

定制IC芯片设计

Virtuoso: 新序曲- Cadence Virtuoso “第18.1 交响乐” 的前奏曲

Cadence Virtuoso is soon presenting a new symphony..."Symphony No. 18.1". Stay tuned…

• less than a min read
Chinese blog , Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , New in EDA , Custom IC Design , Design Planner , Custom IC

Breakfast Bytes

Spectre/Meltdown & What It Means for Future Design 3

I gave an introduction to speculative execution and the vulnerabilities that have…

• 7 min read
meltdown , architecture , processor , Spectre , speculative execution

Breakfast Bytes

What's For Breakfast? Video Preview September 17th to 21st 2018

https://youtu.be/3drxzhMFGD8 Coming from PCB West (camera Sean) Monday: HOT CHIPS…

• less than a min read
Intel , CDNLive India , cascade lake , NVIDIA , Samsung , hot chips , ARM

Verification

Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

Join us on September 14th for a free one-hour webinar on the finer aspects of the…

• less than a min read
uvm , Functional Verification , webinar , Duolos , uvm register layer

Analog/Custom Design

Virtuoso: The Next Overture - Congestion Analysis with a New Perspective

Watch out for the exclusive set of routing features, along with the newly introduced…

• 3 min read
Congestion Analysis , Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Space-based Router , Routing , Virtuoso Advanced Release , Congestion Assistant , New in EDA , Custom IC Design , Virtuoso New Design , Design Planner , Custom IC

Breakfast Bytes

Spectre/Meltdown & What It Means for Future Design 2

I gave an introduction to speculative execution and the vulnerabilities that have…

• 4 min read
meltdown , processor , Spectre , cache , speculative execution , foreshadow

Breakfast Bytes

Spectre/Meltdown & What It Means for Future Design 1

At HOT CHIPS, one of the "keynotes" was actually a panel of what I'll call industry…

• 8 min read
Intel , meltdown , processor , Spectre , cache , ARM , speculative execution , foreshadow

Breakfast Bytes

CDNLive India

CDNLive India took place last week. As usual, I made the long trip from California…

• 5 min read
CDNS - Fix Layout Hompage