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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Digital Design

Pegasus: Get Your Wings: Strong Immunity Makes Pegasus Fault Tolerant

We all know the importance of good immunity and how a good immune system makes you…

• 1 min read
Pegasus Verification System , Fault Tolerance , pegasus , signoff , silicon signoff

Breakfast Bytes

Dover and Cadence: Lessons Learned from SolarWinds

I recently attended a webinar with presenters from Dover, Cadence, and a mystery…

• 6 min read
security , solarwinds , dover , Tensilica

Breakfast Bytes

Tensilica Vision Q8 and P1 DSPs, More AND Less

President George H. W. Bush famously said that he didn't do "the vision thing". Well…

• 5 min read
vision q8 , featured post , vision p1 , Tensilica , vision , neural networks

Digital Design

Low-Power Implementation Training Videos

This blog post describes the Low Power Implementation Flow and IEEE 1801 basic terminologies…

• 1 min read
Low Power , Digital Implementation , Innovus , Power Analysis

カスタムIC／ミックスシグナル

Virtuoso Video Diary: 改善されたReference Historyと新機能Merge HistoryによるIncremental Simu…

Virtuoso® ADE Assembler で以下のような状況に陥ったことはありませんか？ ・Interactiveヒストリに結果がありますが、すべてのスイープ…

• less than a min read
Analog Design Environment , ICADVM18.1 , Virtuosity , Virtuoso Video Diary , japanese blog , Custom IC , IC6.1.8 , Assembler , ADE Assembler

Digital Design

Voltus Voice: Demystifying ESD — 5 Types of Checks to Bump up Your ESD Protectio…

This blog discusses the different Voltus electrostatic discharge (ESD) checks in…

• 4 min read
effective resistance , Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , Power Signoff , electrostatic discharge , current density , Power Integrity , Full-Chip , ESD

Analog/Custom Design

Start Your Engines: Seven Habits of Highly Efficient Mixed Signal Verification E…

This blog shares insights on the seven best practices that should be followed by…

• 8 min read
AMS-Designer , mixed-signal methodology , Start Your Engines , Virtuoso , mixed signal , AMS Verification , mixed-signal verification

Verification

PSS2.0 is Out – Reflections on the Role of a Standard

We all know that a common language is the basis for every collaborative activity…

• 3 min read
portable test and stimulus standard , standardization , pss2.0 , pss

System, PCB, & Package Design 

(P)SpiceItUp: Search by Category, Description, or Function with PSpice Part Sear…

As a designer, your requirement at the early stages of schematic design is quite…

• 4 min read
17.4 , cadence , OrCAD Capture , PSpiceA/D , logical design , Capture CIS , (P)SpiceItUp , 17.4-2019 , OrCAD , Part Search , simulation , Schematic

Breakfast Bytes

Embracing a Zero Trust Security Model

A couple of months ago, the National Security Agency (NSA) published a document titled…

• 4 min read
security , nsa , zero trust

Breakfast Bytes

Brian Jackson Introduces a Mystery Product at IMAPS (Shh, It's OrbitIO)

I have been criticized in the past for calling OrbitIO the "red-headed stepchild…

• 6 min read
system in package , 3DIC , OrbitIO

Verification

CCIX Coherency: Verification Challenges and Approaches

Cache coherency is not a new concept. Coherent architectures have existed for many…

• 2 min read
SoC verification , ccix , PCIe , coherency , CXS

Verification

PSS 2.0 Is Available and Driving Portable Stimulus to the Mainstream!

Three years ago, PSS (Portable Test and Stimulus) specification 1.0 was released…

• 2 min read
Perspec , pss , portable stimulus , verification

Breakfast Bytes

Update: Pointwise, PCIe, RISC-V

This is another of my occasional update posts, covering changes to recent posts that…

• 3 min read
risc-v , pcie 5 , Pointwise , PCIe

RF /マイクロ波設計

μWaveRiders:Cadence AWR ソフトウェアでの強化されたロードプル

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design…

• less than a min read
PCB , source impedance , load impedance , AWR Design Environment , Load Pull analysis , Load Pull data , Load Pull template , RF design , AWR Microwave Office , PA , japanese blog

Breakfast Bytes

Sunday Brunch Video for 18th April 2021

https://youtu.be/afv9_fRCrq8 Made at Target Oakridge (camera Ziyue Zhang) Monday…

• less than a min read
sunday brunch

Analog/Custom Design

Virtuoso Meets Maxwell: Creating Connectivity Between Die and BGA Package for IC…

Before the creation of die and package layout can begin, logical connectivity between…

• 5 min read
IC , package , Footprint , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Package Design in Virtuoso , Allegro Package Designer Plus , BGA , die , OrbitIO , SiP Layout Option , ICADVM20.1 , Ball , Custom IC , bump

RF Engineering

μWaveRiders: Enhancing Load Pull with Cadence AWR Software

The Cadence AWR Design Environment platform V15 offers enhanced load pull capabilities…

• 5 min read
PCB , source impedance , load impedance , AWR Design Environment , Load Pull analysis , Load Pull data , Load Pull template , RF design , AWR Microwave Office , PA

Analog/Custom Design

Virtuosity: What’s New on the Cadence Learning and Support Portal – Virtuoso Layout…

Cadence Learning and Support portal has introduced a new one-stop learning resource…

• 3 min read
Virtuoso , Virtuosity , ICADVM20.1 , Custom IC Design , RAKs , Virtuoso Layout Suite , Custom IC , IC6.1.8 , Virtuoso Layout Suite XL
CDNS - Fix Layout Hompage