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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Embedded Systems Conference Boston 2008

Friday is that last day to get the Early Bird price for the Embedded Systems Conference…

• 1 min read
System Design and Verification , Coverage Driven Verification for Embedded Software , Embedded Systems Conference 2008 , debugging , Jason Andrews , verification

System, PCB, & Package Design 

Techtorials, Demos, Roadmaps ... Poker?

What do these 4 have in common? CDNLive! 2008 San Jose - September 8 - 11, 2008.…

• 2 min read
PCB Layout and routing , CDNLive , DEHDL , OrCAD Capture , PCB Signal and power integrity , Capture CIS , Library and design data management , SPB , High-Density Interconnect , Design Entry HDL , ASA , Allegro System Architect (ASA) , Front-end PCB design , PCB design , AMS simulation , Allegro PCB Editor , Differential Pair Support , ConceptHDL , SPB16.01 , OrCAD PCB Editor , HDI

Digital Design

Understanding Clock Net Markings in SoC-Encounter

I'm happy to report that the Digital Implementation Forums are picking up momentum…

• 3 min read
dbGet , Digital Implementation forums , CTE-TCL , encounter , clocks , saveClockNets

System, PCB, & Package Design 

Breaking down the 'virtual' wall

In the last 3-4 months I have seen, and been involved in, a flurry of discussions…

• 1 min read
IP , cadence , Allegro 16.2 , IC Packaging & SiP design , wirebond profile library , Kulicke & Soffa

System, PCB, & Package Design 

Verifying multi-technology chips-in-a-SiP, fact or fiction?

With everyone talking about System-in-Package (SiP), one challenge that often gets…

• less than a min read
Analog and RF SiP design , IC Packaging & SiP design , IC Package Physical layout and co-design

Verification

iPhone 3G issues - result of HW/SW-co-verification?

In a recent article at cnet, financial analyst said he believes Apple's iPhone 3G…

• 2 min read
Richard Windsor , Infineon 3G chipset , Infineon , System Design and Verification , iPhone 3G , Nomura

Verification

ESL gets a new taker

Interesting High-Level Synthesis review by Bryon Moyer at IC Design and Verification…

• less than a min read
High-Level Synthesis , IC Design and Verification , CDNLive! Silicon Valley 2008

RF Engineering

Tip of the Week: New nport parameter ( dcextrap ) for modeling longer transmission…

There is a new nport parameter, dcextrap, available in MMSIM 6.2.1. The values are…

• 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

System, PCB, & Package Design 

SPB 16.2 release - Constraint Driven HDI PCB Design Flow

Today's SPB 16.2 release is significant for the Cadence Allegro and OrCAD families…

• 3 min read
PCB Layout and routing , NVIDIA , Harris , High-Density Interconnect , PCB design , Allegro PCB Editor , OrCAD PCB Editor , HDI

Verification

Is Concurrent Engineering actually getting worse?

Today I'm taking a few minutes to jot down a few recent observations about the state…

• 3 min read
Concurrent Engineering , System Design and Verification , ISX

Verification

OVM - The Methodology for Enabling an Industry-wide VIP Eco-System

As the leader of the Cadence OVM development team, I was reading Richard Goering…

• 3 min read
SystemVerilog , OVM Professionals Network , Verification methodology , Functional Verification , Open Verification Methodology , OVM , Verification IP modeling , eRM , OVMWorld

System, PCB, & Package Design 

What's good about database parameters and XML import/export?

In the SPB16.01 release, you can now import/export database parameters from Allegro…

• 1 min read
PCB Layout and routing , XML import/export , SPB , PCB design , Allegro PCB Editor , SPB16.01 , OrCAD PCB Editor

RF Engineering

Simulating MOS Transistor ft

One other question that you might ask is, this approach works for bipolars but what…

• less than a min read
bipolar transistor , MOS transistor , RF design

System, PCB, & Package Design 

PartMiner Launches Unique Integration with Cadence OrCAD Capture

Cadence OrCAD Capture is integrated with PartMiner. As a long time EDA librarian…

• 1 min read
Steven Kamin , OrCAD Capture , PartMiner , PCB design

Verification

OVM Leaves the Nest

OK JL , one more marketing post, but this is a good one and even hints at technical…

• less than a min read
Functional Verification , OAG , OVM , OVM Advisory Group , OVMWorld

System, PCB, & Package Design 

What's good about Capture-CIS Digi-Key Integration?

So, what's good about Capture-CIS Digi-Key Integration? Quite a bit actually! This…

• 1 min read
Capture CIS , PCB design , Component Information Portal (CIP) , Digi-Key Integration

Digital Design

See you at CDNLive! Silicon Valley

Are you planning to attend this year's CDNLive! Silicon Valley 2008? Please leave…

• less than a min read
cadence.com community , First Encounter , CDNLive!

Verification

Putting a face on the OVM

As I recently blogged , there appears to be growing buzz over the Open Verification…

• 1 min read
CDNLive , Open Verification Methodology , OVM

RF Engineering

Tip Of the Week: analogLib mtline now has a cross sectional viewer when Type of Input…

Many users have indicated that it is challenging to correctly enter complex transmission…

• less than a min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design
CDNS - Fix Layout Hompage