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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

Breakfast Bytes

DAC Monday: Gaming, IoT Security, State of EDA Industry, Mixed-Signal Lunch, Cooley…

The Design Automation Conference is in Las Vegas this year. If you are here and want…

• 11 min read
DAC , 56dac , Design Automation Conference

Academic Network

How to Show You’re a Verification Engineer?

There is always a need for verification engineers in the microelectronics industry…

• 1 min read
Specman , Cadence Academic Network , verification

System, PCB, & Package Design 

IC Packagers: Dealing with Large Forms in Low Resolution Screens

Our packages and boards are becoming complex and so are the design tasks we perform…

• less than a min read
IC Packaging and SiP , Allegro Package Designer

Digital Design

Need Help with Liberate Commands and Parameters?

Alexa, what is square root of 12547858? Within some nanoseconds, Alexa gives you…

• 1 min read
parameter , Liberate AMS , liberate blog , liberate trio , Liberate LV , Commands , Liberate Variety , Liberate MX , Cadence Help , Digital Implementation , Liberate , Liberty

Breakfast Bytes

Spectre X: Same Accuracy, New Speed

This morning at DAC, Cadence announced the Spectre X Simulator, the latest version…

• 2 min read
Circuit simulation , Spectre , cadence cloud , spectre x

Breakfast Bytes

Sunday Brunch Video for 2nd June 2019

https://youtu.be/T2VZUEW1ucc Made at Protium Hardware Lab (camera Sean) Monday:…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

SI工程师如何分析多千兆位串行链路、内存及接口

作者：Ken Willis 早在2007年，Cadence推动了对IBIS标准的扩展，即算法模型接口（AMI），可以模拟多千兆位串行链路接口。这与通道（与传统电路相对…

• less than a min read
SI , Chinese blog , ddr5 , DDR4 , IBIS-AMI , 中文 , SerDes , Sigrity , 信号完整性 , SI分析与建模

Life at Cadence

Appreciating Our Employees

Recognizing the Outstanding Effort that Makes Cadence Successful Cadence hires the…

• 1 min read
awards

Breakfast Bytes

ESD Alliance CEO Outlook: The Leading Edge, Chiplets, Design Costs, Security, and…

The ESD Alliance (and, before that, its forerunner EDAC) runs a CEO Outlook panel…

• 10 min read
ceo outlook , esd alliance

Verification

Got IP Security Questions? This Luncheon at DAC Has Answers

If you’ve got security on the mind—and in this day and age, who doesn’t?—and you…

• 2 min read
security , DAC , luncheon , DAC 2019 , Accellera

Breakfast Bytes

Embedded Vision: Seeing Round Corners, and Reasoning on Microcontrollers

May is a month that seems to have many things associated with it. "Sell in May and…

• 10 min read
deep learning , Embedded Vision Summit , google , mit media lab , neural network

Verification

DAC 2019 Preview – Multi-MHz Prototyping for Billion Gate Designs, AI, ML, 5G, Safety…

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week…

• 5 min read
security , 5G , DAC , DAC2019 , prototyping , palladium z1 , Safety , tortuga logic , Protium , Emulation , ARM , AI

Analog/Custom Design

Spectre Tech Tips: Spectre APS Save Overview - Part 1

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use…

• 6 min read
save statement , spectre aps , nestlvl , pwr=subckt , save=selected , save=lvlpub , save=allpub , currents=all , subcktprobelvl , Spectre , currents=selected , pwr=devices , Spectre Waveform Writing , pwr=total , pwr=all , save option

Breakfast Bytes

Verific, 20 Years Terrific

What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well…

• 4 min read
verific , Stratus , JasperGold

Whiteboard Wednesdays

Whiteboard Wednesdays - Deep Dive on Simultaneous Localization and Mapping (SLAM…

In this week’s Whiteboard Wednesdays video, Amol Borkar explains how SLAM works.…

• less than a min read
Whiteboard Wednesdays , SLAM

Verification

Thinci Finds Success with the Cadence Verification Suite

On May 23rd, 2019, Cadence announced that Thinci has elected to use the complete…

• 1 min read
ThinCi , Functional Verification , cadence verification suite , success story , verification

The India Circuit

Is The Gig Economy Is Here To Stay?

While the term "gig economy" has been around a long time, it has gained traction…

• 2 min read
gig economy , Re-skilling

Breakfast Bytes

Protium X1: FPGA Prototyping for the Enterprise

Today Cadence announced the new Protium X1 Enterprise Prototyping Platform. The previous…

• 3 min read
protium x1 , System Design and Verification , FPGA prototyping

System, PCB, & Package Design 

IC Packagers: When Being Two-Sided is a Good Thing

With each new generation, demand for smaller, faster, lighter, more efficient is…

• 5 min read
IC Packaging & SiP design , SiP Layout
CDNS - Fix Layout Hompage