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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

Analog/Custom Design

Virtuosity: What's New in Run Plan – Part II

The Run Plan assistant in Virtuoso ADE Assembler has proved to be one of the most…

• 2 min read
Run Plans , custom/analog , Analog Simulation , ADE , Virtuoso Analog Design Environment , calibration , Virtuoso , Analog Design Environment , Virtuosity , Run Plan , runplan , Custom IC Design , Custom IC , Assembler

Breakfast Bytes

Achronix Grew 700% Last Year...eFPGA is a Thing

I don't normally write about the FPGA market. There are three reasons for this. First…

• 6 min read
Intel , embedded fpga , achronix , intel custom foundry , FPGA

Breakfast Bytes

CDNDrive: ISO 26262...Chapter 11

At CDNLive EMEA Robert Schweiger laid out his perspective on the automotive market…

• 5 min read
Automotive , functional safety , CDNLive , CDNLive EMEA , Tensilica , ISO 26262

Whiteboard Wednesdays

Whiteboard Wednesdays - An Introduction to Compute In-Memory

In this week’s Whiteboard Wednesday, Marc Greenberg introduces the concept of “Compute…

• less than a min read
Whiteboard Wednesdays , Memory , processor , DDR , Compute In-Memory

Breakfast Bytes

TSMC: Mobile, HPC, IoT, Automotive...and Packaging

This is the third post about the TSMC Technology Symposium that was held on May 1st…

• 11 min read
Automotive , IoT , TSMC , TSMC Technology Symposium , mobile

Breakfast Bytes

What's For Breakfast? Video Preview May 21st to 25th 2018

https://youtu.be/AmlYRYzIHtY Coming from my office (camera Sean, guest star Alexa…

• less than a min read
accelerating AI , CDNLive , embedded vision , Tensilica , gdpr , MEMS

The India Circuit

Inspiration, Networking and Food For Thought

Recently I had the opportunity to attend the Society of Women Engineers (SWE) Conference…

• 4 min read
society of women engineers , SWE , women leaders

Breakfast Bytes

CDNLive: Testing Times in Munich

Test is the red headed step child of EDA. FinFETs, self-aligned quadruple patterning…

• 9 min read
modus test , CDNLive , Scan test , modus , imec , Test

Academic Network

Status of Verification Education in Academia

Since I’ve started working for Cadence Academic Network three years ago, when talking…

• 3 min read
survey , Cadence Academic Network , Functional Verification , young professionals , Incisive simulator

Breakfast Bytes

Agile Development of Custom Hardware

It was back in 2016 that I first heard about RISC-V, and the Raven implementation…

• 5 min read
bag , chisel , agile software development , waterfall , raven , agile hardware development , UC Berkeley , Agile

Breakfast Bytes

Compromising a Fortune 500 Company...Without Hacking a Thing

Rachel Tobac and Joe Gray opened their talk at RSA by highlighting how important…

• 6 min read
security , rsa conference , rsa , social engineering

System, PCB, & Package Design 

Power-Aware SI DDR4 Simulation: You Have a Choice!

Simultaneous switching noise (SSN) caused by simultaneous switching outputs (SSO…

• 4 min read
Speed2000 , DDR4 , FDTD , power-aware , SystemSI , SSN

Breakfast Bytes

CDNLive EMEA, Driving to the Future

This week it has been the 13th European CDNLive, held in Unertschleißheim in the…

• 7 min read
Automotive , legato , CDNLive , CDNLive EMEA , AI

System, PCB, & Package Design 

Make Reliable Designs That Won’t Fail In The Real World!

Heard about the ongoing recalls in the Automotive and Cellphone industry? Let's address…

• less than a min read
RF , OrCAD Capture , PSPICE , PCB design , simulation

Breakfast Bytes

Digital Marketing in EDA...with No Hands on the Wheel

Years (decades) ago, Robert Townsend, the CEO of Avis, faced a problem. Hertz was…

• 5 min read
google , YouTube , digital marketing , Twitter , adwords , onespin , esd alliance

Whiteboard Wednesdays

Whiteboard Wednesday - Introducing the DFI 5.0 Interface Standard

In this week’s Whiteboard Wednesday, John MacLaren, chairman of the DDR PHY Interface…

• less than a min read
DDR Controller , Whiteboard Wednesdays , DDR PHY

Breakfast Bytes

Legato: Smooth Reliability for Automobiles

In his keynote at ICCAD in 2014, Bosch's VP engineering Peter van Staa said that…

• 4 min read
legato , CDNLive , CDNLive EMEA , reliability

Breakfast Bytes

What's For Breakfast? Video Preview May 14th to 18th 2018

https://youtu.be/T4Pu_l6upso Coming from Englischergarten Munich (camera Andy…

• less than a min read
bag , CDNLive , efpga , chisel , CDNLive EMEA , TSMC , TSMC Technology Symposium , FPGA

Breakfast Bytes

TSMC's Fab Plans, and More

The TSMC Technology Symposium took place recently. I grouped all the process and…

• 5 min read
gigafab , TSMC , TSMC Technology Symposium
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