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Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging

Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant
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Blog - Post List
Latest blogs

SoC and IP

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

From smart cameras to autonomous vehicles and compact edge servers, edge AI is pushing…

• 2 min read
Automotive , Edge AI , Design IP , PHY , DisplayPort , Ethernet standards , USB , Ethernet , PCIe , PCIe Gen3 , SerDes , SerDes IP , PCIe PHY , multi-protocol

Corporate News

Cadence at NVIDIA GTC 2026: From AI Factories to Molecular Discovery

At NVIDIA GTC 2026 , the industry conversation continued its shift beyond incremental…

• 4 min read
GTC2026 , AIEngineering , Engineering Simulation , featured , agentic ai , cadence , AI Factories , Molecular Discovery , semiconductor design , Digital Twins , HPC , AI , Accelerated Computing

Verification

Powering the Future of Memory-Centric Computing with CXL 4.0 VIP

CXL 4.0 Verification IP Now Available! Empowering Advanced AI, HPC, and Data-Centric…

• 2 min read
Verification IP , CXL3.0 , verification

System, PCB, & Package Design 

Streamlining SI/PI Analysis with Clarity 3D Solver’s New ACE Technology

Today’s complex electronic designs, particularly in the context of high-speed interconnects…

• 3 min read
featured , Allegro Package Designer , 3D EM simulation , Clarity 3D Solver , Clarity Automated Channel Extraction , Clarity ACE , allegro x

Physical Systems Simulation (CAE)

BETA CAE Team Announces 2025.2HF1 Software Release

The first Hot Fix of 2025.2 is now available for ANSA, EPILYSIS, META, FATIQ, SPDRM…

• 5 min read
Automotive , Beta CAE

Corporate News

VSORA: Redefining AI Inference with New Silicon Architecture

AI inference is rapidly becoming the largest and most demanding segment of the AI…

• 2 min read
data center , AI inference , designed with cadence

Verification

Cadence VLAB at the Embedded World 2026

Just like every year, the Embedded World took place in Nürnberg in mid-March. It…

• 5 min read
Automotive , virtual platforms , vlab , Embedded World

Verification

UCIe Manageability: The Hidden Control Plane of Chiplet Systems

Chiplet-based architectures are quickly becoming the foundation of next-generation…

• 2 min read
ucie , Verification IP , multi-die , VIP

Artificial Intelligence (AI)

Cadence Brings Chip Verification to the Next Level with AI Agents

By Karl Freund of Cambrian-AI Research , sponsored by Cadence Introduction The…

• 10 min read
artificial intelligence , ChipStack AI SuperAgent , ChipStack , featured , agentic ai , AI

Analog/Custom Design

Animate in Virtuoso Studio: Accelerating Analog Layout Prototyping with It!

The blog introduces Animate in Virtuoso Studio as a powerful analog virtual prototyping…

• 7 min read
IC25.1 , Virtuoso Layout EXL , Layout , Animate , Custom IC Design , Virtuoso Layout Suite , Custom IC

Digital Design

Debugging Unconstrained Paths in Tempus

This blog walks through practical debugging scenarios—from false paths and clock…

• 2 min read
Digital Design and Signoff , timing debug , Timing Optimization , Timing analysis , Tempus Timing Signoff Solution , cadence learning and support

Corporate News

Cadence Recognized as a Platinum Employer on the Where You Work Matters List

We're proud to be named a 2026 Platinum Employer on the Where You Work Matters List…

• 1 min read
news story , featured , Careers , Where You Work Matters , life at cadence

Digital Design

Your Skills Deserve a Passport: Showcase Your Expertise with Digital Badges

In this fast‑changing digital era, every learning milestone you achieve adds a new…

• 3 min read
digital badge , Training and Support , training , training bytes , certification , online training

Verification

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI , verification

System, PCB, & Package Design 

Online Panel: Chiplets and 3D Heterogenous Integration

Microwave Journal and Signal Integrity Journal recently spearheaded an online panel…

• 3 min read
PCB , Sigrity and Systems Analysis , Celsius Thermal Solver , PDN , Allegro X PCB Editor , 3D-IC , Integrity , Power Integrity , IC package design , Signal Integrity , Sigrity , Clarity 3D Solver

Verification

What Makes LPDDR6 a Key Technological Advancement for DRAM Memory Technologies

Low-power DDR SDRAM is one of the most widely used memory types in the semiconductor…

• 4 min read
Storage Technology , Verification IP , Memory , LPDDR , LOW POWER DRAM , JEDEC , DRAM , memory models , Lpddr6

SoC and IP

Understanding the Difference Between a Monolithic SoC and a Chiplet

I am often asked, "What is the difference between a traditional SoC die and a chiplet…

• 7 min read
Design IP , chiplets , OCP FCSA , ip cores , lpddr5x , Arm CSA , CHI-C2C

中文技术专区

喜讯 | Cadence Palladium Z3 与 Protium X3 系统荣膺 2025 全球电子成就奖

在全球电子设计加速演进的浪潮中，Cadence 楷登电子再度以卓越的创新实力赢得行业瞩目。 由全球电子技术领域知名媒体集团 ASPENCORE 举办的全球电子成就奖颁奖典礼于…

• less than a min read
Protium , Palladium

中文技术专区

Cadence Tensilica Vision DSP 助力爱芯元智，提升人形机器人与物联网应用性能

近日，楷登电子Cadence与边缘 SoC 领军企业爱芯元智共同宣布，爱芯元智在其最新的 AX8850N 平台上集成了 Cadence® Tensilica® Vision…

• less than a min read
DSP , IP , Tensilica
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