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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Machine Learning in JasperGold

When I was in Tel Aviv for CDNLive Israel, I sat down with Ziyad Hanna to discuss…

• 4 min read
Jasper User Group , Jasper

System, PCB, & Package Design 

DATA Pulse: Collaborate and Combine Forces – Allegro EDM Team Design

Working in an ECAD design team? Want to control access to certain design elements…

• 2 min read
allegro edm , Team design , PCB design

Breakfast Bytes

Arm TechCon: The Keynotes

Simon Segars opened Arm TechCon with a new look, having discovered that real men…

• 6 min read
Automotive , ARM Techcon , Simon Segars , cloud , mobile , ARM

定制IC芯片设计

Virtuosity：Modgen简介

半导体行业的飞速发展导致对模拟版图自动化的需求不断增长。模拟电路通常使用current mirrors和 differential pairs的结构，其中器件特性的分组和匹配至关重要…

• 1 min read
EAD , Chinese blog , Modgen On Canvas , MODGEN , automation , Automatic Placement , module generation , Module Generator , Layout , Custom IC Design , modgens , Virtuoso Layout Suite , Virtuoso Layout Suite XL

Breakfast Bytes

Sunday Brunch Video for 13th October 2019

https://youtu.be/8BM28qwHyUk Made at Arm TechCon (camera Randy Smith) Monday: What…

• less than a min read
Breakfast Bytes

PCB、IC封装：设计与仿真分析

5G系统的PCB材料和设计要求

即将到来的5G时代迫使设计师对于移动设备和物联网设备的PCB设计进行着重新思考。这些5G系统将使大多数消费者的设备运行速率达到新高度。当我们对电路板提出通信要求时…

• less than a min read
5G , RF , Chinese blog , 系统设计 , PCB Designer , PCB设计 , 中文

Breakfast Bytes

Sensor Fusion and ADAS in TSMC Automotive Processes

At the recent TSMC OIP Symposium, Cadence's Tom Wong presented Sensor Fusion and…

• 4 min read
OIP , Automotive , sensor fusion , TSMC , lidar , radar , Tensilica , vision , camera , ADAS

Breakfast Bytes

The Economist on RISC-V and Indian Semiconductors

Our industry is difficult to understand. Most of us resort to imperfect analogies…

• 8 min read
risc-v , The Economist , CDNLive India , India

Analog/Custom Design

Virtuosity: Device-Level Routing for Advanced Nodes—Tree Route Flow

This is the last blog in the Virtuoso Device-level routing blog series and completes…

• 4 min read
tree routing , structured routing , ICADVM18.1 , Virtuoso Space-based Router , mesh routing , Layout EXL , trunk-to-trunk mesh , Mixed-Signal , Tree Route , Layout Suite , trunk creation , Generate Trunk , Custom IC Design , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

The First Woman to Receive the Kaufman Award

Mary Jane Irwin just got back from a cruise around the Greek islands with her husband…

• 5 min read
Kaufman Award

定制IC芯片设计

Virtuosity：Automated Device Placement and Routing — 基于 WSP 的树型设备布线

此博客概述了 Virtuoso Automated Device Placement and Routing解决方案的最后一步。在本博客中，我将介绍Automated…

• less than a min read
automatic routing , Chinese blog , tree routing , Automated Device Placement , ICADVM18.1 , EXL , Automated Device-Level Placement , VPR , Automatic Placement , Virtuoso Placer , Auto Device P&R , Auto P&R , Tree Route , Virtuoso , Virtuosity , Virtuoso Placement , Placement , Custom IC Design , space based router , Virtuoso Layout Suite EXL , Virtuoso Layout Suite

定制IC芯片设计

Virtuosity：自动设备放置和布线*基础层填充插入

欢迎回到我在Virtuoso Automated Device Placement and Routing 系列的下一篇文章。在advanced nodes上，在运行放置器后…

• less than a min read
automatic routing , device fill , Chinese blog , device fills , Cadence blogs , Automated Device Placement , ICADVM18.1 , Virtuoso Advanced Release , Automated Device-Level Placement , Automatic Placement , Advanced Node , Virtuoso Placer , Auto Device P&R , Layout EXL , Auto P&R , Virtuoso , Virtuosity , Virtuoso Placement , fills , base layer fill , Custom IC Design , Virtuoso Layout Suite , Custom IC

Whiteboard Wednesdays

Whiteboard Wednesdays - The Need for Electro-Thermal Co-simulation

In this week's Whiteboard Wednesdays video, Tom Hackett explains the need for electrical…

• less than a min read
CFD , Celsius Thermal Solver , Whiteboard Wednesdays , 3D IC , FEM , Computational Fluid Dynamics , Thermal Analysis , finite element analysis , FEA

Academic Network

4th Tensilica Day(s!) in Hannover: Doubling the Days, Doubling the Fun

The popularity of the Tensilica day events in previous years (last year's presentations…

• 3 min read
Leibniz Universität Hannover , Cadence Academic Network , academic workshop , academia , EDA , Tensilica , ADAS , neural networks

System, PCB, & Package Design 

IC Packagers: Undoing Your Custom SKILL Commands

Today, we’ll talk about something simple but still important. For all of you who…

• 3 min read
APD , SiP Layout , SKILL

Academic Network

First Ever China Integrated Microsystem Simulation and Modeling Master Thesis Co…

Cadence Academic Network was the exclusive sponsor of the first ever China Integrated…

• 1 min read
university , Cadence Academic Network , academia , Academic Network , university program

Breakfast Bytes

It's Ada Lovelace Day Today

The second Tuesday in October is Ada Lovelace Day (ALD). This is not just a day to…

• 6 min read
analytical engine , ada , ada lovelace , Babbage

Analog/Custom Design

Virtuoso Meets Maxwell: Package PDK in Virtuoso! How Is it even possible!? (Part…

You heard it right! Virtuoso now supports Package and Board level designs; therefore…

• 4 min read
SiP , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , Package Design in Virtuoso , Electromagnetic analysis , Virtuoso , RF design , Custom IC Design , Allegro

Breakfast Bytes

What Is Quantum Supremacy?

There are rumors that Google has achieved quantum supremacy. According to Scott Aaronson…

• 4 min read
quantum computing , IBM , quantum supremacy , google
CDNS - Fix Layout Hompage