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Featured

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
Corporate 1 Oct 2025 • 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
Vinod Khera 28 Sep 2025 • 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 25 Sep 2025 • 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
MBhatnagar 22 Sep 2025 • 3 min read
ucie , Design IP , featured , TSMC , die-to-die
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Blog - Post List

Latest blogs

Analog/Custom Design

Virtuosity: Power Filtering!

Finally, we have filters in the Corners Setup form, Results tab, Outputs tab, Data…

Arja H 5 Oct 2017 • 2 min read
Analog Design Environment , ADE Explorer , Filtering , ADE , Virtuoso Analog Design Environment , Analog Design Environment , ADE Assembler

Breakfast Bytes

EDPS: The Remains of the Day

EDPS is the Electronic Design Process Symposium, historically held in Monterey, but…

Paul McLellan 5 Oct 2017 • 12 min read
deep learning , electronic design process symposium , EDPS , Test , machine learning , design , Breakfast Bytes

System, PCB, & Package Design 

CDNLive China: Interviewing with Allegro R&D VP Saugat Sen

Recently, CDNLive China was held in Shanghai. What are the highlights of PCB Track…

TeamAllegro 4 Oct 2017 • 2 min read
CDNLive , cdnlive china , PCB design , Allegro

Breakfast Bytes

CDNLive Taiwan Automotive Panel

At CDNLive in Taiwan in August, there was a record number of attendees, with about…

Paul McLellan 4 Oct 2017 • 8 min read
Automotive , hsinchu , CDNLive , TSMC , Renesas , cdnlive taiwan , phison , ADAS , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Complexity Optimization of Convolutional Neural Networks…

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, discusses…

References4U 3 Oct 2017 • less than a min read
Whiteboard Wednesdays , convolutional neural networks , CNN

Breakfast Bytes

What's For Breakfast? Video Preview October 9th to 13th 2017

https://youtu.be/SVVE2vM4L6U Coming from Alum Rock Park (camera Carey Guo)…

Paul McLellan 3 Oct 2017 • less than a min read
conformal , China , Chris Rowen , LEC , linley group , semi , grace hopper , vision

The India Circuit

IoT In Smart Factories, Healthcare, Agriculture and More

Last week’s blog ended with some of the IOT trends that Somshubhro Pal Choudhury…

Madhavi Rao 3 Oct 2017 • 4 min read
Automotive , IoT , smart factories , vertical markets , Internet of Things , robotics , ADAS , drones , healthcare , Smart Home

Breakfast Bytes

Scaling Embedded Inference Performance for Deep Learning

Tomorrow it is the Linley Microprocessor Conference and Pulin Desai of Cadence is…

Paul McLellan 3 Oct 2017 • 6 min read
Vision P5 , deep learning , deeplearningmachinelearning , inference , convolutional neural network , training , Tensilica , CNN , neural network , Breakfast Bytes

Breakfast Bytes

AMD's Early Experience with Portable Stimulus

PSS is the Accellera Portable Stimulus Standard. Or I should say proposed standard…

Paul McLellan 2 Oct 2017 • 4 min read
ryzen , AMD , Perspec , pss , portable stimulus , Breakfast Bytes

Learning and Support

Product Page: All Product-Related Information and Knowledge Content in One Place

In the past, some of you have expressed the desire to have all the information and…

MJ Cad 30 Sep 2017 • 1 min read
product , suppport , support resources

Verification

When Arm meets Intel – Overcoming the Challenges of Merging Architectures on an SoC…

As the stakes for winning server segment market share grow ever higher an increasing…

Steve Brown 29 Sep 2017 • 2 min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Breakfast Bytes

Building a Business Model

You know how you sometimes say "the other day" as if it was last week, or maybe the…

Paul McLellan 29 Sep 2017 • 8 min read
business model , pitch deck , garage ventures , reichert , Breakfast Bytes , venture capital

Breakfast Bytes

SJSU School of Cognitive Science

Jim Hogan is a graduate of San Jose State University. Despite the prestige of Stanford…

Paul McLellan 28 Sep 2017 • 7 min read
san jose state university , san jose state , cognitive science , cognitive era , sjsu , Breakfast Bytes

The India Circuit

IOT: Are We There Yet?

One of the invited talks that we had at CDNLive was by Somshubhro Pal Choudhury,…

Madhavi Rao 27 Sep 2017 • 4 min read
hype cycle , CDNLive India , IoT , IOT stack , IOT trends , Internet of Things

Breakfast Bytes

Machine Learning for Higher Performance Machine Learning

The second day keynote at the recent (well, over a month ago, there's been lots to…

Paul McLellan 27 Sep 2017 • 6 min read
tpu , Jeff Dean , google , hotchips , TensorFlow , machine learning , NAE goals , machinelearningdeeplearning , Tensor Processing Unit , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Complexity Optimization of Convolutional Neural Networks…

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, talks…

References4U 26 Sep 2017 • less than a min read
Whiteboard Wednesdays , machine learning , convolutional neural networks , CNN

Breakfast Bytes

What's For Breakfast? Video Preview October 2nd to 6th 2017

https://youtu.be/uT2vXsXHV6s Coming from my car (camera Sean) Monday: AMD…

Paul McLellan 26 Sep 2017 • less than a min read
deep learning , tensiilica , formal , EDPS , sjsu , portabe stimulus standard , Jim Hogan , pss , Formal verification

Verification

Single Core vs. Multi Core: Simulation in Stereo

Latency simulations are the sworn enemy of the verification schedule. A handful of…

XTeam 26 Sep 2017 • 2 min read
Single-Core , Functional Verification , Multi-Core , xcelium , simulation

Breakfast Bytes

SEMI Strategic Materials Conference

Yesterday I wrote about EDPS, which takes place at SEMI. Today, I'm writing about…

Paul McLellan 26 Sep 2017 • 6 min read
China , semiconductor equipment , AMD , semi , moore's law , ARM , Breakfast Bytes
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