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AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
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Blog - Post List

Latest blogs

Academic Network

Using Constraints Generation When Designing Power-Constrained SoCs

If you’re designing SoCs, power is no doubt one of your top concerns—power scheduling…

• 3 min read
constraints generation , Professor Farid Najm , power constrained SoCs , power grid , Power Integrity , voltage drop , power scheduling

Breakfast Bytes

Rob Aitken of ARM Research on System Design

I wrote yesterday of how there is a transition going on as system companies discover…

• 2 min read
SDE , system design , Rob Aitken , system design enablement , ARM , Breakfast Bytes

Academic Network

Why Agile Software Methodologies Can Improve the Chip Design Process

UC Berkeley Professor Borivoje Nikolic sees agile software methodologies as an answer…

• 3 min read
Berkeley engineering , AMS , agile software development , open source , mixed signal , UC Berkeley

Academic Network

Cadence Tech Days at ITMO and MIET

Cadence Academic Network organizes TechDays in Russia to promote leading-edge technologies…

• 1 min read
MIET , Cadence Academic Network , Russia , ITMO

Breakfast Bytes

Applications Down to Transistors: System Design Enablement

Last year Dan Nenni and I wrote a book on the semiconductor industry through the…

• 5 min read
SDE , fabless , moore's law , system design enablement , Breakfast Bytes , foundry

Academic Network

10th Cadence Design Contest 2015 Successfully Organized in India

Cadence India organized the 10th edition of the Cadence University Program’s flagship…

• 1 min read
EDA , Cadence Design Contest , India , university program

Academic Network

Xtensa Design Contest 2015 in India

The Cadence® Xtensa® Design Contest is an initiative of the Cadence India University…

• less than a min read
Cadence Academic Network , Cadence India , Xtensa Design Contest , university program

Academic Network

Cadence Innovus Implementation System is Available to Academia

To support academia using the latest industry-standard tools, Innovus™ Implementation…

• 1 min read
Routing , academia , Innovus , implementation , Placement

Breakfast Bytes

Front-end Design Summit

Wednesday was the annual Front-end Design Summit at Cadence headquarters. This focuses…

• 4 min read
Genus , Encounter Test , manufacturing test , Joules , front end design summit , Test , front end design , Synthesis , power , Breakfast Bytes

Academic Network

Cadence Academic Network - The Next Generation

“University students around the world are using Cadence technology to learn and develop…

• 2 min read
Cadence interns , Cadence Academic Network , EDA , engineering

System, PCB, & Package Design 

What's Good About PCB Allegro Rules Developer and Checker? 16.6 Has It!

You can now leverage the 16.6-2015 release Allegro Rules Developer and Checker .…

• less than a min read
Constraint-driven PCB Design flow , Allegro GUI , Allegro 16.6 , Routing , electrical constraints , High Speed , PCB Editor , High-Density Interconnect , Layout , PCB design , Allegro PCB Editor , differential pairs

Breakfast Bytes

Why Do Layout Designers Say "Stream Out"?

For the same reason we "hang up" our phones. When a layout designer saves a design…

• 6 min read
GDSII , Stream Out , Layout , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—DUT Verification with Cadence VIP

In this week's Whiteboard Wednesday's video, Arindam Guha explains how to quickly…

• less than a min read
DUT verification , Verification IP , Whiteboard Wednesdays , VIP

SoC and IP

Will USB Type-C Connector Replace the 3.5mm Audio Jack?

In the past few days, there have been many posts on the Internet around Apple planning…

• 1 min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , Design IP and Verification IP , USB connector , USB 3.1

Breakfast Bytes

Virtuoso: Advance to 10nm, If You Pass Go Collect $200

There are two major discontinuities in the last couple of process nodes—FinFETs and…

• 5 min read
EAD , FinFets , iPVS , Custom Routing , multi-patterning , Virtuoso , 10nm , modgens , color-aware layout , Breakfast Bytes

System, PCB, & Package Design 

Take Tighter Control Over Your Shape Degassing Patterns with Cadence 16.6 Allegro…

With metal density and balancing requirements getting stricter with every year that…

• 6 min read
Cadence Design Systems , SiP Design , 16.6 , IC package design , APD , Allegro Package Designer , manufacturing , SiP Layout , shapes

Breakfast Bytes

TSMC 3D. Red and Green Glasses Not Required

I have been taking a look at TSMC's 3D packaging technologies. From numerous presentations…

• 4 min read
CoWoS , 3DIC , info-pop , TSMC , InFO , info_s , Breakfast Bytes

Breakfast Bytes

Can You Pass As a Brit? Just Answer 3 Simple Questions

It’s Thankgiving! Happy Thanksgiving if you are reading this on the day. Cadence…

• 9 min read
thanksgiving , lbw , guy fawkes , gunpowder plot , glorious revolution , marmite

Breakfast Bytes

Voltus-Fi: Faithful Custom and Analog EMIR and Power Analysis

First things first. Voltus and Voltus-Fi are two separate products. They are both…

• 3 min read
Voltus-Fi , AMS , electromigration , custom , analog , Voltus , Virtuoso , analog mixed signal , IR drop , power , Breakfast Bytes , EMIR
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